Communications Interoperability



Communications Interoperability

Device

Interface

Detailed Design Document

Version 2.2

Senior Design II 2006

Lafayette College

Table of Contents

1 Definitions 4

2 Team Members: 4

3 LRU Overview – INTERFACE 5

3.1 System Functional Blocks 7

3.2 Inputs 7

3.3 Outputs 8

3.4 UI 8

3.5 Design 8

4 CONDITIONING 10

4.1.1 Inputs 11

4.1.2 Outputs 11

4.1.3 Functional Blocks 11

4.2 COR/Busy Conditioning 12

4.2.1 Inputs 12

4.2.2 Outputs 12

4.2.3 Design 13

4.3 Push-To-Talk (PTT) Conditioning 13

4.3.1 Inputs 13

4.3.2 Outputs 13

4.3.3 Design 13

4.4 ON/OFF Conditioning 13

4.4.1 Inputs 13

4.4.2 Outputs 13

4.4.3 Design 13

4.5 GAIN/BIAS Conditioning IN 14

4.5.1 Inputs 14

4.5.2 Outputs 15

4.5.3 Design 15

4.6 Anti-aliasing Filter 16

4.6.1 Inputs 16

4.6.2 Outputs 16

4.6.3 Design 16

4.7 Reconstructing filter 17

4.7.1 Inputs 17

4.7.2 Outputs 17

4.7.3 Design 18

4.8 GAIN/BIAS CONDITIONING OUT 18

4.8.1 Inputs 19

4.8.2 Outputs 19

4.8.3 Design 19

5 Conversion 20

5.1 Inputs 21

5.2 Outputs 21

5.3 Design 21

6 Detection 23

6.1 Inputs 24

6.2 Outputs 24

6.3 UI 24

6.4 Design 24

6.4.1 Signal Detect 25

6.4.1.1 Inputs 25

6.4.1.2 Outputs 25

6.4.1.3 UI 25

6.4.1.4 Design 25

6.4.2 Connect Detect 26

6.4.2.1 Inputs 26

6.4.2.2 Outputs 26

6.4.2.3 UI 26

6.4.2.4 Design 26

7 ERROR REPORTING 27

7.1 Inputs 27

7.2 Outputs 27

7.3 Design 27

7.4 Inputs 28

7.5 Outputs 29

7.6 Design 29

Table of Figures

Figure 1 – Top Level LRU Diagram 5

Figure 2 – INTERFACE LRU Top Level Diagram 6

Figure 3 – INTERFACE LRU with Highlighted Conditioning Block 10

Figure 4 – Conditioning Top Level Diagram 11

Figure 5 – COR/Busy Conditioning 12

Figure 6 – Conditioning In Circuit 14

Figure 7 – Anti-aliasing Chebyshev Filter 16

Figure 8 - Reconstructing Chebyshev Filter 17

Figure 9 – Gain/Bias Conditioning Out Circuit 18

Figure 10 – INTERFACE LRU with Highlighted Conversion Block 20

Figure 11 – Conversion Top Level Diagram 21

Figure 12 - INTERFACE LRU with Highlighted Detection Block 23

Figure 13 – Detection Block 24

Figure 14 – VOX Circuit 26

Figure 15 - Logic 28

Figure 16 - Error Reporting Logic 29

Definitions

COR/Busy –

Carrier Operated Relay – indicates incoming data on a radio.

Communication device –

Any of eight [8] technology interfaces supported in the system as specified in R003.

Priority –

A communication device designated as priority can talk over all the users of a talk group.

PTT –

Push To Talk – push button interface on radios.

Talk group –

A group of people/technologies with open communication lines with each other. Ex: Police, EMTS and FBI have the ability to communicate to each other, but the CIA cannot communicate with anyone: thus Police, EMTS and FBI are in a talk group.

VOX –

Voice Activated Switch. This Circuitry detects when a valid voice signal is produced by a Communication Device.

LRU –

Line Replaceable Unit

Team Members:

Conditioning:

John Bayard

Scott Curry

Hugh King

Conversion/Detection:

John Bayard

Scott Curry

Edward Kimotho

Hugh King

Zach Silverman

LRU Overview – INTERFACE

The top-level diagram is shown in figure 1. Each communication device must be connected to the CID system via an INTERFACE LRU. This document describes the detailed technical design of the INTERFACE LRU. The INTERFACE LRU is divided into five functional blocks as shown in figure 2: CONDITIONING, CONVERSION, DETECTION, ERROR REPORTING and LOGIC. Each of these functional blocks provides functionality which satisfies one or more of the issued requirements for the CID system. Table 1 shows a matrix of functionalities of the INTERFACE LRU vs. the requirements of the CID system.

The following section outlines the inputs, outputs and design specifications for the entire INTERFACE LRU. Notice that specifications that are dependent on a particular communication device are indicated with the mark DOCD.

[pic]

Figure 1 – Top Level LRU Diagram

[pic]

Figure 2 – INTERFACE LRU Top Level Diagram

|R012 |R011 |R010 |R009 |R008 |R007 |

|Kenwood TK-790 |600 Ω |125 mV |176.7 mV |8.488 V/V |13 kΩ |

|Motorola MaxTrac |600 Ω |600 mV |1.42 V |1.056 V/V |1.8 MΩ |

|Telephony |10 kΩ |- |.447 V |3.35 V/V |42.54 kΩ |

Table 2: Conditioning In Specifications

1 Anti-aliasing Filter

The following section outlines the inputs, outputs and design specifications for the ANTI-ALIASING FILTER. The ANTI-ALIASING FILTER only allows frequencies that are produced by the human voice to pass through. This filter also helps to cut down on the effects of aliasing that result when using an A/D converter. Figure 7 shows the circuitry for the 5th order Chebyshev filter that was implemented in our system.

[pic]

Figure 7 – Anti-aliasing Chebyshev Filter[1]

1 Inputs

• Gained Audio In from Gain/Bias Conditioning In

• Power: 5 Volts, 3.3 Volts, Ground

2 Outputs

• Conditioned Audio In to CONVERSION / DETECTION

3 Design

ANTI-ALIASING FILTER receives Gained Audio In from GAIN/BIAS CONDITIONTING IN. It outputs Conditioned Audio In to CONVERSION/DETECTION. The purpose of the ANTI-ALIASING FILTER is to cut down the bandwidth of Gained Audio In in order to prevent aliasing. Gained Audio In gets filtered using a low pass 5th order Chebyshev filter with a cutoff frequency of 3.9 kHz. A dramatic cutoff of the amplitude of the signal at 3.9 kHz is desired in order to minimize the aliasing effect. Therefore, we opted for the Chebyshev filter, which has a more dramatic amplitude drop-off than other filters at the cost of significant phase shifting in the signal. We chose a 5th order filter to make the drop-off even more dramatic.

2 Reconstructing filter

The following section outlines the inputs, outputs and design specifications for the RECONSTRUCTING FILTER. The purpose of this functionality is to low pass filter the output of the D/A converter. The figure below shows the circuitry for the 5th order Chebyshev filter that was implemented in our system.

[pic]

Figure 8 - Reconstructing Chebyshev Filter[2]

1 Inputs

• Converted Audio Out from CONVERSION

• Power: 5 Volts, 3.3 Volts, Ground

2 Outputs

• Filtered Audio Out to CONDITIONING

3 Design

RECONSTRUCTING FILTER receives Converted Audio Out from CONVERSION. It outputs Filtered Out to GAIN/BIAS CONDITIONING OUT. The purpose of the RECONSTRUCTING FILTER is to low pass filter the output the output of the D/A converter. The RECONSTRUCTING FILTER is identical to the ANTI-ALIASING FILTER, a low pass 5th order Chebyshev with a cutoff frequency of 3.9 kHz. The circuitry is the same as in Figure 6. Again, we accept phase shifting of the signal in exchange for a dramatic amplitude drop at the cutoff frequency.

3 GAIN/BIAS CONDITIONING OUT

The following section outlines the inputs, outputs and design specifications for the GAIN/BIAS CONDITIONING OUT. The purpose of this functionality is to ensure that the audio signal is amplified and biased to meet the communication device specifications.

[pic]

Figure 9 – Gain/Bias Conditioning Out Circuit

1 Inputs

• Filtered Audio Out from Reconstructing Filter

• Mic Ground from communication device

• Power: 5 Volts, 3.3 Volts, Ground

2 Outputs

• Conditioned Audio Out to Communication Device

3 Design

GAIN/BIAS CONDITIONING OUT receives Filtered Audio Out from the Reconstructing Filter. The signal on Filtered Audio Out is then gained and biased according to the specifications dictated by the particular technology of the communication device (refer to Table 3). There is a jumper on the board that changes the impedance values in the circuitry to accommodate different communication devices. Figure 8 depicts shows the circuitry.

The following table shows the pertinent conditioning specs about the three specified technologies:

|Technologies |Impedance |Max Voltage RMS @ 60% |Max Voltage |Required Gain |R1 |

| |(R3) | | | | |

|Kenwood TK-790 |600 Ω |5 mV |11.7 mV |.0078 V/V |786.1 Ω |

|Motorola MaxTrac |600 Ω |80 mV |188.56 mV |.126 V/V |14.4 kΩ |

|Telephony |10 kΩ |- |.447 V |.298 V/V |42.54 kΩ |

Table 3: Gain/Bias Conditioning Out Specifications

Conversion

The following section outlines the inputs, outputs and design specifications for the CONVERSION block. The task of the CONVERSION block is to convert the audio signal from analog to digital for routing to the HUB LRU, and then back from digital to analog for the communication device. Figure 10 highlights the CONVERSION block and shows all the inputs and outputs. Figure 11 shows a more detailed diagram of the CONVERSION block, showing some of the signal routing within the block.

[pic]

Figure 10 – INTERFACE LRU with Highlighted Conversion Block

[pic]

Figure 11 – Conversion Top Level Diagram

1 Inputs

• Conditioned Audio In from CONDITIONING

• Audio Out from LOGIC

• Clock (3.3V, 100kHz) from LOGIC

• CS (3.3V, 10kHz) from LOGIC

• CEDAC (3.3V, 10kHz) from LOGIC

• Power: 5 Volts, 3.3 Volts, Ground

2 Outputs

• Converted Audio In to LOGIC

• Converted Audio Out to CONDITIONING

3 Design

CONVERSION converts Conditioned Audio in from CONDITIONING from an analog signal into a serial digital data signal. CONVERSION also converts Audio Out from HUB LRU from a digital audio signal to an analog audio signal.

The A/D conversion is performed by the Texas Instruments TLC0831C chip. It is an 8-bit A/D converter with a chip select (CS). CS informs the chip when to start converting Conditioned Audio In into digital audio. The TLC0831C chip is running on a 100 KHz clock from the HUB LRU, and outputs a 0-5V digital signal serially to a Level Shifter (Texas Instruments CD4504BE). The Level Shifter converts the 0-5V digital signal to a 0-3.3V digital signal Converted Audio In and sends it to LOGIC.

The D/A conversion is performed by the combination of a shift register and a parallel D/A. Audio Out is a serial representation of digital audio and comes from LOGIC and go to the shift register (Texas Instruments SN74HC164N). The shift register converts the serial signal Audio Out into an 8-bit parallel representation using the same clocking rate that is used by Analog to Digital Converter. The parallel representation of the digital audio goes to the parallel Digital to Analog converter (Analog Devices AD558JN). CEDAC enables the Digital to Analog converter to convert the parallel digital audio into analog audio. When the Digital to Analog converter sees a falling edge in the active low CEDAC signal, it updates Converted Audio Out that is sent to CONDITIONING.

Detection

The following section outlines the inputs, outputs and design specifications for the DETECTION functional block. The tasks performed by the DETECTION block are twofold: to determine if a communication device is connected to the system, and to detect if a particular device has an active audio signal. Figure 12 highlights the DETECTION block and shows all the signals coming in and going out of it. Figure 13 is a more detailed diagram of the DETECTION block.

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Figure 12 - INTERFACE LRU with Highlighted Detection Block

[pic]

Figure 13 – Detection Block

1 Inputs

• Conditioned Audio In from CONDITIONING

• Conditioned COR/busy signal (3.3V logic) from CONDITIONING

• Conditioned ON/OFF(3.3V logic) from CONDITIONING

2 Outputs

• Signal Detect (3.3V logic) to LOGIC

• Connect Detect (3.3V logic) to LOGIC

3 UI

• Signal Detect Status LED

• Connect Detect Status LED

4 Design

DETECTION notifies the HUB and user when a communication device is currently connected and when a connected device is producing an audio signal. Signal Detect and Connect Detect are forwarded from detection to LOGIC. Connect Detect signifies when a device is psychically connected to the INTERFACE LRU. Signal Detect signifies that a connected device is transmitting an audio signal.

1 Signal Detect

The following section outlines the inputs, outputs and design specifications for the SIGNAL DETECT functional block. The task of this block is to detect if a particular device has an active audio signal.

1 Inputs

• Converted Audio In from CONVERSION

• Conditioned COR/Busy (3.3V logic) from CONDITIONING

2 Outputs

• Signal Detect (3.3V logic) to LOGIC

3 UI

• Signal Detect Status LED

4 Design

DETECTION notifies the HUB LRU unit when a connected device is currently producing an audio signal via Signal Detect. Signal Detect is determined in different manners depending on the technology of the communication device; if the communication device is a radio with a COR/busy signal, DETECTION forwards COR/busy via Signal Detect. However, in the case of a technology, such as telephony, where no COR/busy signal is available, the detection block determines whether the line is active based on the amplitude of the signal on the line. To do this, a simple VOX circuit is implemented. The choice between VOX implementation for telephony or the COR/busy signal for radio technology is determined by the user via a jumper.

One effect from using a VOX implementation is that there is not an immediate indication when a line is idle after continued use. All VOX circuits wait a specific amount of time to determine whether the line is busy: in the case of our VOX circuit, this determination time is approximately 1.5 seconds. After 1.5 seconds of the line being idle, the Signal Detect signal goes low again, indicating the line is open.

[pic]

Figure 14 – VOX Circuit

2 Connect Detect

The following section outlines the inputs, outputs and design specifications for the CONNECT DETECT functional block. The task of this block is to determine whether a communication device is connected to the INTERFACE LRU.

1 Inputs

• Conditioned ON/OFF (3.3V logic) from CONDITIONING

2 Outputs

• Connect Detect (3.3V logic) to LOGIC

3 UI

• Connect Detect Status LED

4 Design

Connect Detect is determined by Conditioned ON/OFF, which is taken from the communication device connected to it. If the user is using voice-over IP technology, a digital signal is supplied from the computer to the INTERFACE LRU, indicating that it is connected. The Connect Detect status LED on the INTERFACE LRU indicates when a communication device is connected. The HUB LRU is alerted when a device is connected via Signal Detect.

ERROR REPORTING

The following section outlines the inputs, outputs and design specifications for ERROR REPORTING. ERROR REPORTING monitors DC voltage levels to ensure voltage signals are not too high, as high signals could possibly jeopardize individual components.

1 Inputs

• Level 1.5V (3.3V logic) from CONDITIONING

• Level 1.8V (3.3V logic) from CONDITIONING

• Level 3.3V (3.3V logic) from CONDITIONING

• Power: 5 Volts, 3.3 Volts, Ground

2 Outputs

• Compared Level 1.5V (3.3V logic) to LOGIC

• Compared Level 1.8V (3.3V logic) to LOGIC

• Compared Level 3.3V (3.3V logic) to LOGIC

3 Design

The error philosophy for the INTERFACE LRU involves a static test of the voltage level at various points in the CONDITIONING and DETECTION blocks. The purpose of ERROR REPORTING is to ensure that all components are functioning properly. In order to ensure this, there must be minimal dependency between the INTERFACE LRU and the other LRUs. ERROR REPORTING circuitry is isolated from the other circuitry on the INTERFACE LRU so that it does not interfere with the other audio and control signals on the INTERFACE LRU.

Diagnostic is sent from the HUB LRU to the INTERFACE LRU, instructing it to start checking for errors. This switches the INTERFACE LRU to a testing mode. In this mode, Audio In from the communication device is turned off and a nominal DC voltage signal is sent to the CONDITIONING block via GainedAudioOut. This signal should be between 1.5V and 1.8V. If GainedAudioOut is out of this range an error signal is asserted. An error signal is also asserted it Conditioned Audio Out is less than 3.3V. LOGIC

The following section outlines the inputs, outputs and design specifications for the LOGIC functional block. The task of the LOGIC block is to route digital signals on the INTERFACE LRU. Figure 13 zooms in on the LOGIC block, showing the inputs and outputs of the block.

[pic]

Figure 15 - Logic

4 Inputs

• Converted Audio In from CONVERSION

• Audio Out from HUB LRU

• Connect Detect (3.3V logic) from DETECTION

• Signal Detect (3.3V logic) from DETECTION

• Pushbutton (3.3V logic) from HUB LRU

• Compared Level 1.8V (3.3V logic) from ERROR REPORTING

• Compared Level 1.5V (3.3V logic) from ERROR REPORTING

• Compared Level 3.3V(3.3V logic) from ERROR REPORTING

• Diagnostic (3.3V logic) from HUB LRU

• Clock (3.3V, 100kHz) from HUB LRU

• CEDAC (3.3V, 10kHz) from HUB LRU

• CS (3.3V, 10kHz) from HUB LRU

• Power: 5 Volts, 3.3 Volts, Ground

5 Outputs

• Converted Audio In to HUB LRU

• Audio Out to CONVERSION

• Connect Detect (3.3V logic) to HUB LRU

• Signal Detect (3.3V logic) to HUB LRU

• Pushbutton (3.3V logic) to CONDITIONING

• Error Signal 1(3.3V logic) to HUB LRU

• Error Signal 2 (3.3V logic) to HUB LRU

• Diagnostic (3.3V logic) to ERROR REPORTING

• Clock (3.3V, 100kHz) to CONVERSION

• CEDAC (3.3V, 10kHz) to CONVERSION

• CS (3.3V, 10kHz) to CONVERSION

6 Design

[pic]

Figure 16 - Error Reporting Logic

The LOGIC is implemented on two GALs. We use the 20-pin ATMEL 16LV8 chip in its simple mode.

The first GAL is used to implement the error philosophy. Connect Detect, Signal Detect, Compared Level 1.5V, Compared Level 1.8V, Compared Level 3.3V and Diagnostic signal are sent into the GAL. Figure 15 shows the logic implemented to generate Error Signal 1.

This GAL is also used to implement the multiplexer that routes Converted Audio In; if the LRU is in diagnostic mode, Converted Audio In is routed to the CONVERSION block, while if it is in standard operating mode, it is routed to the HUB LRU.

The second GAL is used to clearly define the voltage levels for Clock, CEDAC, CS, Converted Audio In, Audio Out and Pushbutton. This clears out noise from the signals, and leave a crisp 0 or 3.3V depending on if the logic is low or high.

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