UNIVERSITY OF CALIFORNIA



UNIVERSITY OF CALIFORNIA

College of Engineering

Department of Electrical Engineering and Computer Sciences

Last modified on February 12, 2003 by Dejan Markovic (dejan@eecs.berkeley.edu)

Prof. Jan Rabaey Homework #3 Solutions EECS 141

Spring 2003

Problem 1 – Inverter Delay Calculation

1A For inverter A, prove that when the output voltage characteristics satisfy the following relation: VM[pic](VOH + VOL)/2, the delay for output to rise from VOL to VM (or fall from VOH to VM) can be modeled as tp = 0.69ReqCL, even if the output swing is not rail – to – rail. Here Req is the equivalent resistance of the device driving the output, and CL is the load capacitance on the output node.

The capacitor charging process can be modeled as:

[pic],

where V(∞) is the capacitor voltage at the end of the charging

(when t = ∞ ), and V(0) is the capacitor voltage at the beginning

of the charging (when t = 0).

In this problem during the output low to high transition, V(0) = VOL, V(∞) = VOH, solve:

[pic] ( tp = 0.69ReqCL

1B Evaluate the propagation delays of the two inverters using the VTC data we attained from last homework’s analysis. Here measure the delay as the time between VIN = VM and VOUT = VM. Use the switch approximation analysis of the MOS transistor presented in class (Req = (RM + RVOH) / 2) to estimate tpLH, and same for tpHL.

Inverter A:

a) Calculate Req during pull down (OK if you subtracted off IDS(M2)):

At VIN = VDD = 3.3V, VOUT = VOH = 2.24V, M1 is in linear region.

[pic]

R(VOH) = VOH / ID = 9.5KΩ

At VIN = VDD = 3.3V, VOUT = VM = 1.27V, M1 is in linear region.

[pic]

R(VM) = VM / ID = 7.6KΩ

Pull down Req = (R(VOH)+ R(VM))/2 = 8.55 KΩ

b) Calculate Req during pull up:

At VIN = 0, VOUT = VOL = 0.374V, M2 is saturated.

[pic]

[pic]

R(VOL) = (VDD - VOL) / ID = 52KΩ

At VIN = 0, VOUT = VM = 1.27V, M2 is saturated.

[pic]

[pic]

R(VM) = (VDD -VM ) / ID = 144KΩ

Pull up Req = (R(VOL)+ R(VM))/2 = 98 KΩ

c) tpLH = 0.69 RupCL = 10.1ns

tpHL = 0.69 RdownCL = 0.88ns

tp = (tpLH + tpHL)/2 = 5.49ns

Inverter B:

a) Calculate Req during pull down:

At VIN = VDD = VOH = 3.3V, , Mn is saturated.

[pic]

R(VOH) = VOH / ID = 38.9KΩ

At VIN = VDD = 3.3V, VOUT = VM = 1.68V, Mn is in linear region.

[pic]

R(VM) = VM / ID = 24.8KΩ

Pull down Req = (R(VOH)+ R(VM))/2 = 31.85 KΩ

b) Calculate Req during pull up:

At VIN = VOUT = VOL = 0, Mp is saturated.

[pic]

R(VOL) = (VDD - VOL) / ID = 32.4KΩ

At VIN = 0, VOUT = VM = 1.68V, Mp is in linear region.

[pic]

R(VM) = (VDD -VM ) / ID = 21.7KΩ

Pull up Req = (R(VOL)+ R(VM))/2 = 54.1 KΩ

c) tpLH = 0.69 RupCL = 5.6ns

tpHL = 0.69 RdownCL = 3.3ns

tp = (tpLH + tpHL)/2 =4.45ns

1C Verify tpLH and tpHL using HSPICE. (Note that there may be slight difference between your SPICE and hand calculation results, because approximations are used in our hand analysis. You can think about the reason for the discrepancy while you are not required to do so in this homework.)

The SPICE deck used to calculate the tPLH and tPHL of inverter A:

_____________________________________________________________________________

.model nmos NMOS VTO=0.6 GAMMA=0.5 PHI=0.6 KP=20E-6 LAMBDA=0.05

.model pmos PMOS VTO=-0.6 GAMMA=0.5 PHI=0.6 KP=7E-6 LAMBDA=0.1

m2 out vd vd 0 nmos w=1.2u l=1.2u

m1 out in 0 0 nmos w=3.6u l=1.2u

vin in 0 PULSE(0 3.3 5n 10p 10p 40n 80n)

vdd vd 0 3.3

c1 out 0 150f

.tran 1n 100n

.meas t1 trig v(in) val=1.27 cross=1 targ v(out) val=1.27 cross=1

.meas t2 trig v(in) val=1.27 cross=2 targ v(out) val=1.27 cross=2

.option post=2 nomod

.op

.end

______________________________________________________________________________

Inverter A: HSPICE tpLH = 5.03ns (Hand tpLH = 10.1ns)

HSPICE tpHL = 0.87ns (Hand tpHL = 0.88ns)

HSPICE tp = (tPLH + tPHL)/2 = 3ns (Hand tp = 5.49ns)

Inverter B: HSPICE tpLH = 4.7ns (Hand tpLH = 5.6ns)

HSPICE tpHL = 2ns (Hand tpHL = 3.3ns)

HSPICE tp = (tpLH + tpHL)/2 = 3.35ns (Hand tp = 4.45ns)

Here comes the fun part: although the HSPICE takes more delay factors into account including the parasitic capacitances of the devices which should lead to larger delay, it actually produces much smaller delay numbers than our hand calculations. Why is that?

Let’s look at the tPLH of inverter A which has the discrepancy of almost a factor of 2 as an example. The Device Resistance vs. Vds curve of M2 in inverter A is plotted as below. It can be easily observed that the two points of M2 resistance at VOUT = VOL = 0.374V and VOUT = VM = 1.27V match our calculations perfectly. However the non linear increase of resistance with Vds leads to the pessimistic results in our Req calculation — the actual Req should be smaller than the linear average result that we got. Therefore the subsequent delay calculation turns out to be pessimistic than the reality.

1D Explain why M2 is sized to be much smaller than M1 in the first (all-NMOS) circuit? Briefly comment on that. What disadvantages on performance does the inverter with NMOS-load have compared to the CMOS inverter?

M1 has to be sized much larger than M2 in this circuit because during the pull down operation the M1 must be strong enough to pull the output voltage down to VOL, which should be close to 0. However small M2 results in the weak pulling up drive, so that the VTC of this inverter is very unsymmetrical with delay on one transition almost 10 times larger than the other.

Though the average propagation delays of the two inverters are similar, the unsymmetrical timing characteristics of inverter A are very undesirable in achieving good delay path balancing. Also the long pull up time to VOH brings even degraded noise margin or long settling time, which worsen its performance.

Problem 2 – Computing the MOSFET Capacitances

2A It is always good to get a feel for design rules in a layout editor. Fire up max with the mmi25 (0.25 um) technology file (this is the default setup). Place a minimum sized NMOS transistor and examine the dimensions. The layers are listed and shown below in Figure 2a. Determine and list the following:

a. Minimum Transistor Length

b. Minimum Transistor Width

c. Minimum Source/Drain Area

Please list the design rules you come across that lead to your results.

Rules are:

i) Poly minimum width = 0.24 µm

ii) CT minimum width = 0.3 µm

iii) CT_NDIF to NFET MIN, spacing = 0.22 µm

iv) ALL_POLY_DIF MIN CT enclosure = 0.14 µm

Results:

a. L = 0.24 µm

b. W = 0.3 µm + 2(0.14 µm) = 0.58 µm (0.60 µm acceptable)

c. Ldrain = 0.3 µm + 0.14 µm + 0.22 µm = 0.66 µm

AD = AS = Ldrain * W = 0.66 µm * 0.58 µm = 0.383 µm2 ≈ 0.4 µm2

2B We desire a minimum sized CMOS inverter with a symmetrical VTC (VM=VDD/2) in the mmi25 technology. Calculate the desired size for the pull-up PMOS transistor, with the NMOS transistor minimum sized as in 2A.

d. PMOS Transistor Length

e. PMOS Transistor Width

f. PMOS Source/Drain Area

Assume the following:

VDD = 2.5V, VM = 1.25V, use data in Table 3-2 in the textbook

Since in this problem VDD is not high enough for PMOS to work in vel. saturation region, the accurate solution of transistor size ratio can be derived by using the saturation equations for PMOS drain current in VM calculation. Also the channel length modulation effect can be included:

[pic]

The gate lengths will be identical. Therefore,

Wp = 3.23 * 0.58 = 1.87 µm, AD = 1.23 µm2

However the equation 5.5 from the textbook can also be applied as an approximation (VDD = 2.5V is close to the higher VDD with can drive the transistors in vel. saturation at VM, and the channel length modulation can be ignored for a first order analysis):

[pic]

Then the following results are also acceptable:

Wp = 3.48 * 0.58 = 2.02 µm, AD = 1.33 µm2

The solution followed will be derived with the approximation ratio assuming vel. saturation for both transistors. However you are absolutely correct if you are using the saturation equation for PMOS drain current together with the channel length modulation effect analysis, which should be more accurate.

2C Using the minimum size inverter from 2B, determine the input capacitance (i.e. the load it presents when driven), which is the total load capacitance that the inverter presents. Please calculate the capacitance during a transition. Use data in Table 3-5 in the textbook

*Hint: Consider the Miller effect

You have three capacitances per transistor to consider on an inverter for input capacitance, gate to bulk, gate to source and gate to drain. Cox = 6.0fF/µm2

Cin = Cgs12 + 2Cgd12 + Cgb12

(The factor of 2 is due to Miller effect)

During the transition M1 & M2 operate in either linear or saturation region, thus

Cgb = 0.

Cgd12 = Cgdo + Cgdc

Cgs12 = Cgso + Cgsc

PMOS:

Overlap cap.

Cgdop = COWP = (3.1 fF/µm)*(2.02 µm) = 0.606 fF

Cgsop = COWP = (3.1 fF/µm)*(2.02 µm) = 0.606 fF

Channel cap.

Saturated Cgdcp_sat = 0, Cgscp_sat = 2/3 (CoxLpWp) = 2.02 fF

Linear Cgdcp_lin = Cgscp_lin = 1/2 (CoxLpWp) = 1.52 fF

NMOS:

Overlap cap.

Cgdon = COWn = (3.1 fF/µm)*(0.58 µm) = 0.174 fF

Cgson = COWn = (3.1 fF/µm)*(0.58 µm) = 0.174 fF

Channel cap.

Saturated Cgdcn_sat = 0, Cgscn_sat = 2/3 (CoxLnWn) = 0.595 fF

Linear Cgdcn_lin = Cgscn_lin = 1/2 (CoxLnWn) = 0.443 fF

The channel capacitances of MOSFET change with the operation region. Thus in this problem the equivalent input capacitance is calculated as the average capacitance during the transition.

For an input high-to-low transistion ( Vout from 0 to Vdd/2),

| |Operation Region 1 | |Operation Region 2 |

|PMOS |Saturated | |Saturated |

|NMOS |Linear | |Saturated |

At operation region 1,

Cin1 = Cgsop + Cgson + 2(Cgdop + Cgdon) + 2 (Cgcdp_sat + Cgcdn_lin) + Cgcsp_sat + Cgcsn_lin

= 5.689 fF

At operation region 2,

Cin2 = Cgsop + Cgson + 2(Cgdop + Cgdon) + 2 (Cgcdp_sat + Cgcdn_sat) + Cgcsp_sat + Cgcsn_sat

= 4.955 fF

Taking average of the two operation regions,

CinHL = (Cin1 + Cin2)/2 = 5.322fF

During an input low-to-high transistion,

| |Operation Region 1 | |Operation Region 2 |

|PMOS |Linear | |Saturated |

|NMOS |Saturated | |Saturated |

At operation region 1,

Cin1 = Cgsop + Cgson + 2(Cgdop + Cgdon) + 2 (Cgcdp_lin + Cgcdn_sat) + Cgcsp_lin + Cgcsn_sat

= 7.495 fF

At operation region 2,

Cin2 = Cgsop + Cgson + 2(Cgdop + Cgdon) + 2 (Cgcdp_sat + Cgcdn_sat) + Cgcsp_sat + Cgcsn_sat

= 4.955 fF

Taking average of the two operation regions,

CinLH = (Cin1 + Cin2)/2 = 6.225fF

NOTE: The Miller effect is included in the calculations because the inverter in question is not loaded by the external load. If the inverter is driving very large load, the Miller multiplication can be excluded in the input capacitance for the delay calculation.

2D Using the same g25 model as you worked with in homework 2, verify your results in part c by determining the total input capacitance in a high-low and a low-high transition with HSPICE and comparing with your total capacitance in part c.

Input SPICE Deck for Measuring CinLH:

____________________________________________________________________________

HW #3, prob. 2d Measuring CinLH of Inverter

*****begin DEFINITIONS*****

.lib '/home/aa/grad/huifangq/g25b.mod' TT

.param vddp = 2.5

.param ln_min = 0.24u

.param lp_min = 0.24u

*****end DEFINITIONS*****

VDD vdd 0 vddp

IIN 0 in 1u

M1 out in vdd vdd pmos L=lp_min W=2.02u AD=0.383p AS=0.383p

M2 out in 0 0 nmos L=ln_min W=0.58u AD=0.383p AS=0.383p

.ic v(in) = 0

.meas t1 when v(in)='vddp/2' cross=1

.meas CinLH param='1u*t1/(vddp/2)'

.options post=2 nomod

.op

.tran 0.1ns 15ns

.END

______________________________________________________________________________

SPICE calculates: CinLH = 5.74 fF CinHL = 4.88 fF

Hand calculations: CinLH = 6.22 fF CinHL = 5.32fF

2E Determine VIH, VIL, NMH, and NML.

*Hint: The 2 parameters r and g vary proportionally with transistor width. The equations given are derived with the minimum width in mind. (Please refer to Eq’s 5.3 and 5.10 in the textbook for r and g)

First find r using eqn. 5.3 of the reader and then g using eqn. 5.10. Remember to account for the size difference by applying direct ratio.

r = 1.94 g = 30.2 VM = VDD/2 = 1.25V

Then use equations 5.7 to solve:

VIH = VM + (2.5-VM)/g = 1.29V VIL = VM – VM/g = 1.21V

NMH = VDD – VIH = 1.21 V NML = VIL = 1.21V

Problem 3 – Generating a Voltage Transfer Characteristic

3A Assume we use these FETs to create a CMOS inverter. Using this family of PMOS and NMOS curves, graph the VTC, and calculate VM, VIL, and VIH.

The VTC below is plotted from SPICE using the inverter circuit comprised of FETs that generates the above I-V curves. Yours should have been drawn by hand using the intersections of the NMOS and PMOS curves. The shape of your VTC should look like this SPICE plot, just with much less points connected together. The method to drawn the VTC from curves is the same as elaborated on the solution of homework 2 problem 3.

If you’re interested, the input SPICE Deck used to create the family of curves and the VTC seen below in Figure Solutions.2d can be found at the end of this solution. Note that those are old files. So if you want to run them you’ll need to first modify the model link to the existing one.

The simplest way to determine the input voltages is to note the points on the curve where the slope is –1, which was defined in class. VM can be determined by noting the point of intersection between the VTC and a linear curve with slope = 1.

VIL = 1.1V

NML = 1.1V

VIH = 1.4V

NML = 1.1V

VM = 1.25V

a) If we increase the W/L ratio of the pull-down NMOS (leaving the PMOS size fixed), in which direction will the VTC shift?

Strong NMOS ( The VTC will shift to the left.

b) If instead, we increase the W/L ratio of the pull-up PMOS (and leave the NMOS the original size), in which direction will the VTC shift?

Strong PMOS ( The VTC will shift to the right.

c) Please explain how the resizing in b) and c) will affect the above I-V curves in each case and give an intuitive explanation of how this affects the VTC of each.

If we increase the W/L of an NMOS or PMOS, it moves the I-V curves up (higher magnitude of current for same input voltage). As such, a larger NMOS gives more pulldown “strength,” while a larger PMOS gives more “pullup” strength.

Input Spice Deck for Prob. 3, NMOS Id-Vout Characteristics:

_______________________________________________________________________

Hw #3, Prob. 3 - NMOS (Dietrich Ho, 9/4/2000)

.lib '~ee141/MODELS/g25.mod' TT

vdd vdd 0 2.5

vin vin 0 0

vds vds 0 0

m1 vds vin 0 0 nmos w=1.0u l=0.25u

.dc vds 0 2.5 0.1 vin 0 2.5 0.5

.plot LX4(m1)

.option post=2 nomod

.END____________________________________________________________________

Input Spice Deck for Prob. 3, PMOS Id-Vout Characteristics:

_______________________________________________________________________

Hw #3, Prob. 3 - PMOS (Dietrich Ho, 9/4/2000)

.lib '~ee141/MODELS/g25.mod' TT

vdd vdd 0 2.5

vin vin 0 0

vds vds 0 0

m1 vds vin vdd vds pmos w=3.0u l=0.25u

.dc vds 0 2.5 0.1 vin 0 2.5 0.5

.plot LX4(m1)

.option post=2 nomod

.END____________________________________________________________________

Input Spice Deck for Prob. 3, VTC:

_______________________________________________________________________

Hw #3, Prob. 3 - VTC (Dietrich Ho, 9/4/2000)

.lib '~ee141/MODELS/g25.mod' TT

vdd vdd 0 2.5

vin vin 0 pulse 0 2.5 0 5n 5n 10n 10n

m1 vout vin vdd vdd pmos w=3.0u l=0.25u

m2 vout vin 0 0 nmos w=1.0u l=0.25u

.dc vin 0 2.5 0.1

.tran 1n 50n

.option post=2 nomod

.END___________________________________________________________________________

-----------------------

ndif

ct

nfet

poly

Figure Solutions.2d

+

VC

–

CL

Req

+

E

–

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