1) DUT Pin 1 Orientation correct and labeled



DESIGN CHECKS WHEN YOU THINK YOU’RE DONE WITH A PCB DESIGN

1) DUT Pin 1 Orientation correct and labeled. All IC pin 1 labeled.

2) All components are cleared from Component keep out areas.

3) Top and Bottom Keep out areas are identified (Component, via, and Route keep outs are known)

4) Check Component (DUT) Mounting hole clearances. (Soldermask clearance)

5) Calculate the countersink, and counterbore clearances in Excel Calculator.

6) Have targets on all layers

7) Have fiducials (4 on top, and 4 on bottom) and labeled with silkscreen. (Use Cadence symbol FID50, and label them FID1, FID2, etc,...)

8) All four corner mounting holes need to be at least 125 in the X, and 125 in the Y distance from board edge. (ix = 200, and iy = 200 is perfect) Usually a 125 NPTH. Use (MTG_4_40_116D_250C footprint, and this schematic symbol STANDOFF_4_40_187Dx1p625L

SILKSCREENS

1) TI,(Customer), Logo on top silk with their part number Copy right date is correct.

2) TI Top Silkscreen has: (ACE Logo, Anti Static logo, TI Texas Logo, and S/N NUMBER BOX)

3) Check Top & bottom silk screens (REF DES, comp outlines, Misc. text, Component polarity)

3) ACD Title block and Revision number correct per customer's input.

4) IC pin number 1 are present on Both top and Bottom silkscreens. (Tantilum Caps with a + Polarity sign.) ---> BGA Corner pins Labeled (Tss)

5) The TI silkscreen board name has Rev 1.0, or whatever the Rev should be.

ETCH / ROUTING

1) Signals are 3x the trace width for trace to trace spacing.

2) Check each layer for off-board text. (and count, 1of 10, etc,..) Tilte block off board text matches the layerstack name.

5) Rerun Cadence Summary Drawing report 100% routed. No Dangling lines

6) Overlay plane data with an adjacent trace layer to see hole to trace clarances are OK. (Keep signal returns away from pin voids!!)

7) Add the ACD part number on Bottom etch. Ex.(ACD# TIACE-XXXXX-01)

8) Run DBCheck and review DRC totals again.

9) Add TI (Ticket) number to outer layer etch

DRILL DATA

1)Make sure the drill data is up to date; overlay fab drawing with pads on layer1.

2) Check and include all drill tolerances in Fab drill table.

3) For Allegro designs, Look for duplicate drill symbols on Fab drill chart. Combine drills when possible

PLANES

1) Verify all Thermal clearances. Use 50mil Anti-etch board Outline relief on planes. 25 in and 25 out (At least 25 mil splits on planes)

2) Do a Negative plane check. Turn on DRC's like this: Open up the Constraint manager > Hit the " Design Constraints" button right above the "Electrical constraints Sets.." button > Next, turn on the "negative plane islands" option > ok > exit

3) Turn on the following and see the plane clearances and via voids.

Display Plated holes, Filled pads, Cline endcaps, Thermal pads, and grids

4) Delete unused isolated island shapes.

SOLDERMASK

1) Both top and bottom soldermask has a 100 mil line, or 50 mil line following the board outline. Make sure that your components are inside this area. Look at all other Soldermask clearances, and add more clearance if possible

2) If you have outer copper fill shapes, add some tented vias in that area.

3) Double check your two top solder masks, socket clearance, or solder dut option.

FAB DRAWING

1) Look at Fab drawing checklist notes. Dimension From x 0,0 and to the neartest mounting hole. Call out stuff like Diff Pairs and their impedance requirements, Other single ended traces and thier impedance requirements,Fine pitch(.5mm) BGA's, Only label the layers that have the certain impedance requirement.

2) Every board needs the LPI Silkscreen note. "APPLY NON-CONDUCTIVE LPI SILKSCREEN OR EQUIVALENT ON BOTH SIDES. COLOR: WHITE."

3) Add "VIEWED FROM PRIMARY SIDE" OR "PRIMARY SIDE VIEW" below the dimensioned board.

4) Set all Drill symbols to be 100 in height.

5) No Duplicate symbols for different size drills.

6) ADD your Layerstack.

7) Include any detail drawings

8) Make sure the title block date is correct, because the subclass for this is different.

9) Update the Fab note where: Gold is to be 2 to 6 Microinches of Gold Min . Nickel should be 100 microinches thick.

10) Fab note 2 should be class 2 (two places).

11) Add any Diff pair, Single ended Impedance requirements.

12) Review board dimensions, and detail call outs.

13) Review which holes need to be silver filled and polished flat.

14) Add a Dimension from Origin to nearest hole.

15) Add the 0,0 dimension.

16) Add board thickness with proper tolerance.

More checks below:

1) Check for Anti-pad clearance on Test points and any through hole Component. (Minimum annular ring from pin to shape is 12 mils; preferred is 15)

2) Make sure that you don't have the Board outline in any layer that doesn't need it. Examples (Tss, Bss, all positive layers) ****(You will need it for Top and Bottom Mask layers, BASSY, TASSY, and all Negative plane layers) (**Not on Negative layers when you do the Gerber RS274x option)

3) Make sure that if you created a symbol to overlay the mask layer over the silkscreen layer to see if the silkscreen is not covered by mask. (Leave a 5 to 10 mil airgap from silk to mask.)

SPECIAL CHECKS

1) Review any Special areas once more for any violations.

2) Purge all Unused Padstacks

3) Rename the Ti board name to the ACD Name.

4) Remove all DRC's from the saved artwork film control views

5) Set the Board Outline to be Zero width.

6) ACD Film control layers named correctly. See the "ACD Film Naming convention" note.

7) Look to see if you have plane shapes on outer layers, (Top and bottom), if you do, then use the Via012D_tent vias. All other vias can use the Via012D padstack.

8) Add this note to the Fab "Process notes" IF AND ONLY IF YOU HAVE A REGULAR BGA SOCKET; NOT USED IF YOU HAVE A THRU HOLE SOCKET: "All 6.0 mil holes to be silver filled and polished flat."

9) Delete all "Clip" properties.

10) Same Net DRC set to "On"

11) Give All the Text Photo widths of at least 5 mils.

12) Check the board revision on the ACD title block, Tss, assembly drawing.

13) If this board goes to ACD, make sure that you have the ACD footprint for the 0402 components.

14) Make the Tsmk 50 mils thick and check to see if any components, or silkscreen will be in violation.

16) Check your Cross section to see if it is set correctly. (Plane, Conductor, Postive, or negative layers.)

17) Create The ASSYT and ASSYB layers.

18) If you are working on a second revision; always update symbols.

19) If you have layers with routing and planes it is good to do a Delete Islands on those layers to delete all floating copper planes.

20) Check your BGA via Thermals. They should be set to 1 mil dia thermal for full contact. (Or use positive planes)

21) If working on a respin, update all symbol foot prints.

22) Run your NC Drill legend again.

23) If you have a Socket BGA, make sure that you add the Positional tolerance notes in the FAB drawing.

24) Check the socket Lead length clearance for SSE boards to adjust board thickness.

25) Don't have any Anti-etch on negative plane layers in Artwork setup.

(You can have anti-etch, but don't have it visible in your artwork film control)

26) Check Fab Note: Max Warp and twist note to be .0075 inches per inch.

27) If you get a re-spin board from India, or anywhere and it has Tented vias all over the board, make sure that Melissa knows that it is not Flying probe testable.

28) Look for any Tsmk, Bsmk, or Tss Bss Shapes that touch any pads, because CAM software deletes it when they clip shapes.

29) Do a Palm Search for RoHS to get the latest Fab note.

30) Run your Gerbers through the CAM viewer to confirm special trace widths.

31) Review Artwork film Positve and negative Gerber Setup.(Shape bounding box, etc,..)

32) Check 0,0 FAB DWG Origin

More checks below:

1) Make sure that you don't have power nets / traces routing under crystals.

2) Make sure that you use the correct Jumpers per the board thickness. (See this note for more info: "New CAPTURE library symbols".)

3) Review any special note that may be in PKG\Geo Display_Top, or any other layer.

4) Review Diode and cap polarity of the Silkscreen symbol.

5) If you have a PM_DUT board for Albert Lew, make sure that all the RS and RB signals are not tied to the gnd plane at the header pins. (Add the "no_shape_connect" property at the header pin.)

6) Check all plane layers for the Route Keep in Stub; get rid of any stubs caused by the Route Keep in.

7) If you have a board name with "EVM", then don't add this text to the top Silkscreen name, just leave this "EVM" out of the name on silkscreen.

8) Don't place Testpoints too close to Jumers. (Ex: between jumpers becasue they are difficult to get to.)

9) Don't move the diode silk symbol too far away from the diode body. Put the symbol either directly above or below the component body.

10) Make sure that your NC Drill 2:5 is setup correctly under Manufacture > NC > NC Drill > NC Paramters button

11) All Diode silkscreen symbols should be placed directly beside or under the shape symbol.

12) Make sure to use the NC Drill Customization tool!! NEVER manully edit any Drill tolerance on the drill chart!

13) Use a separate via when you are told to flood the external shapes with vias. (Use the Via012D_tent)

14) If your board requires it, add a fab thieving note under process notes:

"ADD Thieving as needed on external layers .150 inches away from existing features."

15) Double check the Cable connections on any header or various connector parts to see if there is room for the plastic cable connection.

16) Purge unused constraints

17) If you don't have a BGA on your design, then change fab note 5 to read as follows: "WITH A MINIMUM ANNULAR RING OF .002" It would be a minimum annular ring of .001" with a BGA.

18) If you have an edge SMA that has etch going to board edge, add note 8 from the BRF6300 design. (Maybe make a new Fab note clip file for this?)

19) Add the TI Code (Ticket) number on etch.

20) Add teardrops to all .4mm pitch BGAs

21) If you have a small board design and you would like to let the boardshop panel it for you, then use this clip file:

"PANEL_NOTE" Clip file in this directory:

C:\Mario_DIR\PLOT_Clip_FILES\FAb_Clip

22) If your fiducial is on an external flood plane, then use the DYN_CLEARANCE_OVERSIZE = 5 mil property to clear the pin to shape airgap distance.

23) Check for any parts that cut into the board and verify all plane layer cut-outs in those areas. (Or check for any board cut-outs, and planes in general.)

24) Make sure that your dimension lines of the fab are lined up. Hal will get you if you don't.

25) Periodically do a search for Autosave board files and delete them when you have some free time.

26) Run a "Net single pin and No Pin" Which will create a "Single Pin and No Pin Net" Report, this tells you that the pin has a net name but no other connection.

27) Run the dangling lines report seperate from the summary report.

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