Performance - JMU



PCI Bus Architecture

CS 350: Computer Organization

Sections 1 and 2

Spring 2004

Prepared by: Lauren Greenfield

Matthew Pozun

Lindsay Stenger

Olivia Ting

Table of Contents

Introduction………………………………………………………………………………1

History…………………………………………….………………………………………1

Performance…………………………...…………………………………………………2

§ How PCI Compares to Other Buses........................................................................3

§ Voltage Requirements..............................................................................................3

§ Features...................................................................................................................4

Plug and Play………………………………………...…………………………………...4

§ Requirements for Full Implementation....................................................................4

§ Tasks it Automates...................................................................................................4

How PCI Works…………………………………..……………………………………...5

Other Types of PCI……………………………………..………………………………..6

The Future of PCI and PCI Express……………………………..…………………….7

Conclusion…………………………...…………………………………………………...9

Bibliography…………………………...………………………………………………..10

Introduction:

There are many different types of buses on a motherboard. What their purposes are, how they work, and how they originated are all details that will give a base of understanding and a more in depth knowledge of the PCI bus. A computer bus is used to transfer data from one location or device on the motherboard to the central processing unit where all calculations take place. A computer bus has two different parts: the address bus and the data bus. The data bus transfers the actual data while the address bus transfers information about where the data should go.

Some of the main buses inside a computer are the ISA bus, MCA bus, EISA bus, VLB bus, PCI bus, AGP bus, USB bus, mini PCI bus, and PCI-X bus. The PCI bus is what this paper will concentrate on, explaining the details of its history, its performance and how that compares to other buses. We will explain how Plug and Play plays a roll in the use of the PCI bus, how the PCI bus works, engage in a brief discussion of the other types of PCI, and the future of the PCI. PCI bus is based on the technology of the ISA (Industry Standard Architecture) bus and the VL Bus.

History:

The Peripheral Component Interconnect bus was introduced by Intel in 1992 and was revised in 1993 to version 2.0 and then again in 1995 to version 2.1. It started out as a 32-bit bus that later became the 64-bit bus that it is today. The one thing about this bus that made it even greater than other buses that were developed was that this bus was developed as an industry standard. It was not designed by one specific company that only wanted to use it on their computers, but rather it was made for all computer companies to use.

When installing an ISA device you had to set the jumpers and dip switches so that the device would work properly. The development of PCI made it much easier to install devices for people that did not understand a lot about computers. This is because the manufacturer could give you software for the device. The user would place the device in the PCI slot, start the computer, and then install the software the manufacturer provided.

The PCI bus is a combination of the old ISA bus developed by IBM and the VESA Local bus. ISA originated as an eight bit bus and then became sixteen bits and became known as ISA. ISA is capable of transmitting at sixteen MBps, which is capable of doing most applications even today.

VESA local bus (named after Video Electronics Standards Association) is 32 bits wide and can transmit at the speed of the local bus, which is typically the speed of the processor. The problem with the VL-bus is that if you connect too many devices into this bus it can start to introduce latency in the processor.

The PCI bus provides direct access to system memory for the devices that are connected to it, but all of these are connected through a bridge that then connects to the front side bus. Based on this configuration it can provide higher performance without slowing down the processor. The PCI bus originally worked at 33 MHz to 66 MHz. PCI uses a small number of pins because the hardware multiplexes by sending more than one signal over the same pin. PCI devices can be either 3.3 volts or 5 volts.

Figure 1 – Diagram of the Motherboard bus system (Tyson, 2001c)

PCI did not become famous until Microsoft came out with Windows 95 operating system and used Plug and Play technology. PCI did not take off then because it needed an operating system that could handle Plug and Play, and that really utilized the concept of the PCI bus.

Performance:

In any computer environment, performance of the system is crucial. Computers are used in military to medical environments, which at times require that the components of the system be as fast as possible. The PCI is one of the fastest buses available today at a reasonable cost with speeds ranging up to 4.3 GBps, in PCI-X 2.0, which is the most current revision (Quatech, 2004b). The following sections go over such topics as how the versions of PCI that we use compare to older popular buses, what the voltage requirements are for cards designed with PCI in mind, and features of PCI that help it operate as well as it does.

How PCI Compares to Other Buses:

Over the years, as technology has changed, different buses of varying speeds have been used to build computers. Two buses that are still prevalent today are the Industry Standard Architecture (ISA) bus and Peripheral Component Interconnect (PCI) bus, which has several revisions on the original PCI theme. A good overview of the aspects of a couple PCI variants, and ISA buses is featured in table 1 below.

|Bus Type |Bus Width |Bus Speed |MB/sec |Advantages |Disadvantages |

|ISA |16 bits |8MHz |16 MBps |low cost, compatibility, |low speed, Jumpers & DIP |

| | | | |widely used |switches. becoming obsolete |

|PCI |64 bits |133 MHz |1 GBps |very high speed, Plug & |incompatible with older |

| | | | |Play, dominant board-level|systems, |

| | | | |bus |can cost more |

|CompactPCI |64 bits |33MHz |132 MBps |designed for industrial |lower speed than PCI, need |

| | | | |use, hot swapping/Plug & |adapter for PC use, |

| | | | |Play, ideal for embedded |incompatible with older |

| | | | |systems |systems |

Table 1: How PCI compares to other buses (Tyson, 2004a; Quatech, 2004c)

As can be seen in the table above the PCI technology that is available today can reach speeds of 1 GBps which is high for today’s standards, but even this is changing. Soon, as stated above, PCI-X 2.0 will be showing up more and more, bringing with it speeds into the 4.3 GBps range. Overall, PCI has been the best bus for connecting devices such as Ethernet cards and USB cards, because it is very fast (Quatech, 2004b).

Voltage Requirements:

When PCI was originally developed all boards that plugged into the PCI slot had to be able to accept 5V power supplied by the motherboard. Over the years, only the power, which was provided by the motherboard, stayed the same (Quatech, 2004a).

The amount of power supplied to the board has changed greatly. After the original 5V, an option for only 3.3V was developed and considered optional, and later, with PCI 2.3, 3.3V became required making 5V obsolete (Quatech, 2004a).

To make sure that the correct voltage travels to the card different arrangements of the gold fingers on the bottom of the card exist (these fingers are known as the key). Because of these different keys Universal PCI slots have been developed which support both 5V and 3.3V cards (Quatech, 2004a).

Features:

Due to features present in the PCI bus, PCI is the fastest general Input/Output bus used in Personal Computers today. Three specific features that make this possible are: (1) PCI has Burst Mode (allows multiple sets of data to be sent after an initial address has been received), (2) PCI is also capable of full Bus Mastering, which leads to improved performance by allowing devices on the PCI bus to take control and perform direct transfers (Kozierok, 2001c). (3) Lastly, PCI also has some High Bandwidth Options that have allowed the speed of PCI to be continually increased (Kozierok, 2001a).

Plug and Play:

Plug and Play is a feature that allows the user to add a new piece of hardware to the computer and have it recognized and configured to work on the system. Plug and Play is important in a PCI system because these systems were the first to make Plug and Play popular (Kozierok, 2001b). The Plug and Play system was developed by Intel with Windows 95 offering the first system-level support for Plug and Play (Tyson, 2004b).

Requirements for Full Implementation:

In order for your Personal Computer to fully implement Plug and Play it needs to have three things:

• Plug and Play BIOS – these BIOS do two things. First, they allow Plug and Play to operate on the computer and they retrieve configuration information about Plug and Play devices that are already installed on the system.

• Extended System Configuration Data (ESCD) – A file on the system that contains information about Plug and Play devices that are already installed on the system.

• Plug and Play operating system – This requirement can be fulfilled by any operating system that supports Plug and Play. Various operating systems that fulfill this requirement would be Windows 95/98/ME/2000/XP. The operating system is needed because it has Plug and Play handlers that will complete the configuration process that was started in the Plug and Play BIOS.

(Tyson, 2004b)

Tasks It Automates:

The Plug and Play feature automates four tasks that previously had to be done by hand or with an installation utility that had to be provided by the hardware manufacturer. These four tasks include:

• Interrupt Requests (IRQ) – An IRQ is a request from the hardware device to the Central Processing Unit (CPU) that indicates that the hardware has information that needs to be done. Originally, each device connected to the computer needed its own IRQ to operate, but PCI changed that. PCI connects at the bus bridge, which allows multiple PCI devices to use a single IRQ line.

• Direct Memory Access (DMA) – PCI devices are set up so that they can directly access the system memory without needing to ask the CPU first.

• Memory Addresses – Plug and Play automatically assigns memory addresses to different hardware devices to ensure that the devices will have the necessary system resources to allow it to operate properly.

• Input/Output (I/O) Configuration – The last task that Plug and Play automates is determining what ports the devices will send and receive information on.

By providing these automatic capabilities, Plug and Play was able to make PCI the bus of choice (Tyson, 2004b).

How PCI Works:

All buses hold specific standards for their bus architecture. The standards are based on MHz, Mbps, Bits, and Voltage. MHz (or Megahertz) is the speed of the data transfer. MBps (Mega Bytes processed per second) is the transfer rate, measuring how much data can be transferred within a period of one second. A higher Mbps will indicate a faster device. The Bits specification is similar to the number of lanes on a highway that can accommodate traffic. 32 bits will represent 32 lanes on the highway, which can handle a lot of cars. If there are more bits, then the more data it can accommodate. Finally, the Voltage standard is the amount of electrical energy it takes to do its work. The lower the voltage, the better, as it would satisfy the new “Green PC” energy requirements. The PCI is one of the best buses out there, comparable to ISA, EISA, and VESA, as shown on table 2 (Advanced Horizons, 2003):

| |ISA |EISA |VESA |PCI |

|MHz |8.3 |8.3 |33 |33 |

|MBps |8.3 |33 |160 |132 or 264 |

|Bits |16 |32 |32 |32 or 64 |

|Voltage |5 |5 |5 |3.3 or 5 |

Table 2: PCI bus standards compared to other bus standards

Some computer motherboards can have anywhere from four to six PCI slots. Because the PCI is usually controlled by Windows software, it has the capability to be automatically configured once a new device card has been inserted into a PCI slot. Before being able to understand how PCI works, it must first be properly installed into the computer. The following steps explain how to properly install a new external device into the computer.

1. With the computer turned off, take off the computer case, and then insert the card into an empty PCI slot on the motherboard.

2. Put the case back on, and with all the cables and cords properly plugged in, turn on the computer.

3. The computer system Basic Input/Output System (BIOS) will initiate the Plug and Play (PnP) BIOS.

4. The PnP BIOS will scan the PCI bus for the hardware by sending out a signal to any device connected to the bus, asking for identification.

5. The card will respond with its identification and its device ID will be sent back to the BIOS through the bus.

6. PnP checks the Extended System Configuration Data (ESCD) to make sure the configuration data already exists for the card. If the card is new, then there will be no data for it.

7. PnP will assign and Interrupt Request Line, Direct Memory Access, memory address and Input/Output settings to the card, then stores the information in the ESCD.

8. When the Windows software loads, it will check the PCI bus and the ESCD to see if there is new hardware. If there is new hardware, Windows will alert the user that new hardware has been found and will identify the hardware.

9. Windows will determine the type of device and attempt to install its driver. The operating system may ask the user to insert a disk containing the driver or direct it to where the driver is located. In the event that Windows is unable to determine what the device is, it will provide a dialog window so the user can identify the hardware and load its driver.

(Tyson, 2001c)

As an example, a user installed a new sound card and wanted to record audio from an external source connected to the sound card. After installing the sound card and setting up the audio software, the user begins recording. The audio sound will enter the sound card through an external audio connector, and the sound card will convert the analog signal to a digital signal. The digital audio data is then, carried across the PCI bus to the bus controller, which determines which device on the PCI device has the priority to send data to the central processing unit (CPU) as well as whether the data will go directly to the CPU or to the system memory. Because the sound card would be in recording mode, the bus controller will assign a high priority to the data coming from the sound card. It will send the sound cards data over the bus bridge to the system bus. The system bus will save the data in system memory. When the recording is complete, then it will be up to the user to save the data from the sound card on either the hard drive, or will remain in memory for additional processing (Tyson, 2001c).

Other Types of PCI:

Originally, PCI had the 5Volts standard, but with the continual attempt to improve the PCI bus, there have been various improvements made to the PCI standards. Some of the most improved releases include PCI 2.3, PCI-X, and PCI Express (which will be mentioned in the next section).

PCI 2.3 was an advancement from the original PCI in regards to the Volt standard. The lowering of the Volt usage to 3.3V satisfied the “Green PC” energy requirements. One small problem that had been created when this came out was the fact that some people still wanted to have both Voltage capabilities. As a result UniversalPCI boards were created so that allowed the motherboards to be used for both a 3.3V and 5V cards. The frequent use of 3.3V cards however, has made the use of 5V cards obsolete (Quatech, 2004b).

PCI-X was an even bigger advancement from PCI 2.3. The PCI-X has had two releases. The first release doubled the maximum clock frequency that can be used by PCI devices, (from 66MHz to 133MHz). This enabled communications to go at speeds over 1 Gigabyte per second. This improved the efficiency of the PCI bus as well as the devices that would be attached to it. It was mostly developed for applications such as the Gigabyte Ethernet, Fiber Channel, and any other Enterprise server applications. Its second revision (known as the PCI-X 2.0) increased both the speed and performance. The maximum clock frequencies jumped to 266 MHz and 533MHz, which support data transfers of up to 4.3 Gigabytes per second of bandwidth. It also adds additional features that help to increase the systems reliability in minimizing errors at high speeds (Quatech, 2004b).

The biggest, and still most deliberated improvement will be the PCI Express. There is still speculation of all its new capabilities, but it has been said that it will take the Input/Output connectivity into the next decade. Its description will be discussed in this following section.

The Future of PCI via PCI Express:

The future of PCI is going to be seen within the next year. The traditional PCI architecture and its variants have reached their limits and have created a bottleneck in the flow of data. This is why the next generation of the PCI architecture, called PCI Express, is under development and will soon be available in the marketplace. PCI SIG (PCI governing board) is developing the architecture so it will last into the future. They are allowing for this because they designed the architecture to achieve the following goals:

• Support multiple market segments

• Backwards compatible

• Scalable performance

• Advanced features including Quality of Service (QoS), power management, and data integrity

The first goal the new PCI architecture, to support multiple market segments, will come into play much in the same way the original PCI architecture did. The design of PCI Express allows for it to unify the multiple I/O technologies today into one common platform that will be able to accommodate the different hardware requirements of the many I/O devices. The PCI technology reached its usefulness in various I/O devices such as graphics and data transfer rates so manufacturers had to turn to other architectures such as AGP, PCI-X, Intel Hub link, etc… to achieve the performance desired. This led to computers having no real industry standard (Bhatt 2002). This in turn lead to an increase in the price of hardware because specific hardware would have to be engineered based on the applications needed to be accomplished. With the specifications of the PCI Express architecture, manufacturers can produce hardware based on a single architecture that allows the same performance (and higher) that could be achieved by the other architectures, therefore lowering the costs of production and design of hardware because all their resources could go towards the one architecture.

PCI Express offers scalable performance through the redesigned 1st layer of the architecture, known as the physical layer. The physical layer offers this scalability by allowing devices to choose their lane width to carry data on. It also allows for changes in the implementation of this layer based on future technologies without affecting any of the higher levels. Meaning once technology increases progress hardware developers will only have to worry about changing the implementation of this level, without having to rewrite any of their other code for the device. The scalability on the lane width for data flow is automatically setup by the device, without the involvement of firmware or software. Each of these transfer lanes consists of two, low voltage, differentially driven pairs of signals; a transmit pair and a receive pair. Each lane has an embedded data clock that uses an 8bits by 10bits encoding pair to achieve high data transfer rates and is initially set to 2.5 Giga-transfers/s per lane, per direction providing 200MB/s of communication and has the ability to increase with advancements of silicon technology up to 10Giga-transfers/s per lane, per direction (the theoretical transfer limit of copper) (Bhatt 2003). The lane widths that are available are x1, x2, x4, x8, x16, and x32, which allows for a device to have a transfer rate of up to 80 Gb/s initially and a theoretical limit of 320 Gb/s. All the actions taken on this layer are not noticed by any of the higher layers, which allows for upgrades in this section to take place without any changes to current software.

Data integrity is dealt with in the 2nd layer of the architecture known as the Data Link Layer. This layer’s primary job is to ensure data integrity and order of the data packet. It generates a CRC and sequence number for every data packet sent, and allows for every detected error to be corrected. One of the key advantages PCI Express has over PCI occurs within this layer. PCI Express uses no sideband signaling, all the information is transmitted in-band which reduces the pin count. Since the links carry both payload data (Transmission Link Packet, TLP) and management data (Data Link Layer Packet, DLLP), the management and payload data are interspersed allowing flow control to take place. Using the DLLP the device will know if it has enough resources to handle the TLP and waits until it does before it sends a packet so that none of it will be lost. Also the DLLP is able to tell the device whether the data has been received properly and if not, it will be re-sent. Once data has passed through this layer it then gets transmitted to the next layer known as the transaction layer (PLX Technology).

The 3rd layer known as the transaction layer allows PCI Express to maintain complete software compatibility, giving it complete backwards compatibility. The implementation of this layer functions exactly as it does in the legacy PCI Architecture. This makes the new devices appear to the operating system and other software as a normal PCI device. This is one big advantage of the architecture, allowing the end user to use their existing software without having to upgrade as well as allowing hardware manufacturers to reuse their old proven and tested code in the new architecture.

Another technology being developed alongside the PCI Express architecture is called Advanced Switching (AS). The goal of AS is to create advanced features for PCI Express that were not available with other PCI architectures. AS is a logic circuit that works to take the load off of the main bandwidth of the system. It accomplished this goal by allowing devices to communicate directing with one another when no information is needed to be retrieved from memory thus freeing up the bandwidth used by these types of communications (Bhatt, 2003). This bandwidth is now free to be used by memory relevant calls, allowing more communication to occur. The figure below shows the switch as a separate element, however it can be built into the host bridge to do the same operation.

[pic]

Figure 2: picture from Bhatt 2002

Conclusion:

The PCI bus has played an important role in the evolution of the personal computer throughout the past decade. This architecture provided the end user with affordable, powerful, and easy to install and configure upgrades. However because of the limitations of the PCI architecture, and the numerous other architectures on the market today PCI is becoming less feasible as an option for the computing industry. PCI SIG (the governing body of PCI) has noted these problems and devised a plan to ensure that a new version of PCI will be around for another decade. PCI Express is slated to replace the growingly obsolete PCI architecture. It will provide as its predecessor did, an affordable powerful way of connection IO devices to a computer.

Bibliography

Advanced Horizons (2003). “Buses Explained ISA VESA PCI.” URL:

Bhatt, Ajay V. (2002). “Xilinx Solutions for PCI Express” URL:

Bhatt, Ajay V. (2003). “Creating a third generation IO interconnect.” URL:

Kozierok, Charles (2001a). “PCI Bus Performance.” Peripheral Component Interconnect (PCI) Local Bus. URL:

Kozierok, Charles (2001b). “PCI Plug and Play.” Peripheral Component Interconnect (PCI) Local Bus. URL:

Kozierok, Charles (2001c). “PCI Bus Mastering.” Peripheral Component Interconnect (PCI) Local Bus. URL:

PLX Technology (2003). “PCI Express Overview.” URL:

Quatech (2004a). “PCI, UnaversalPCI, and Voltage Requirements.” PCI Bus Overview. URL:

Quatech (2004b). “PCI-X.” PCI Bus Overview. URL:

Quatech (2004c). “Bus Comparison.” URL:

Tyson, Jeff (2004a). “Along Comes PCI.” How PCI Works. URL:

Tyson, Jeff (2004b). “Plug and Play.” How PCI Works. URL:

Tyson, Jeff (2001c). “How It Works.” How PCI Works. URL:

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