ULTRAD-1280 Series
ULTRAD-1280 Series
High Performance PCI Bus Data Acquisition Boards
Models ADDA1280DX Dual 40 MHz 12-bit A/D + Dual D/A
AD1280DX Dual 40 MHz 12-bit A/D
DA1280DX Dual 20 MHz-12-bit D/A
ADDA1280SX Single 40 MHz 12-bit A/D + D/A
Product Specification
May 15, 2001
Ultraview Corporation
34 Canyon View, Orinda, CA 94563
(925) 253-2960
Fax (925) 253-4894
e-mail : support@
URL :
copyright c 1998, 1999, 2000, 2001 Ultraview Corporation
TABLE OF CONTENTS
1. Warranty 4
2. Model Descriptions 5
2.1 MODEL ADDA1280DX 5
2.2 MODEL ADDA1280SX 5
2.3 MODEL AD1280DX 5
2.4 MODEL DA1280Dx 5
3. Specifications 6
3.1 A/D Converters 6
3.2 D/A Converters 6
3.3 High Speed Vectored TTL Inputs 7
3.4 High Speed Vectored TTL Outputs 7
3.5 Low Speed Software-Programmed TTL Outputs 7
3.6 General 7
3.7 Physical 8
4. Hardware Architecture 8
4.1 Analog Inputs 8
4.2 Analog Outputs 9
4.3 I/O connector 9
4.3.1 Trigger Input Line 11
4.3.2 Event Input Line 11
4.3.3 TTL_In[7..0] / External Clock 11
4.3.4 TTL_Out[3..0] 12
4.3.5 Miscellaneous programmed TTL outputs (RSSTB, RSCLK, RSDAT) 12
4.4 Front-End Mezzanine Board Interface Connections 12
4.5 LED Indicators 12
4.5.1 Run LED 12
4.5.2 RDY ( Ready ) LED 12
5. Low-level Software Interface 13
5.1 PCI Configuration Header 13
5.2 Ultrad Control Register 14
5.2.1 Software_Run (write only) 14
5.2.2 Buffer_Wrap (write only) 15
5.2.3 Interrupt_Enable (write only) 15
5.2.4 Double_Speed (write only) 15
5.2.5 AD_DA (write only) 15
5.2.6 RSSTB (write only) 16
5.2.7 RSCLK (write only) 16
5.2.8 RSDAT (write only) 16
5.2.9 TimeStamp_Test (write only) 17
5.2.10 Sample Interval (write only) 17
5.2.11 Board Interrupting (read only status bit) 18
5.2.12 Board Stopped (read only status bit) 18
5.3 Data Representation in Memory 18
5.4 Time Stamp Function 20
6. Hardware Installation and Setup 21
6.1 PCIBus Installation 21
6.2 Software Installation for Windows 2000 or Windows NT TM 22
6.3 Software Installation for Windows 95TM, 98 or Windows METM 22
6.4 Software Installation for Solaris 2.6,7,8 (Sparc Platform Edition)TM 22
6.5 Software Installation for Solaris 2.6 (Intel Platform)TM 23
7. APPENDIX A. FRONT-END MEZZANINE BOARD INTERFACE 24
7.1 Front-end Mezzanine Interface Pinout 24
Warranty
Ultraview Corporation hardware, software and firmware products are warranted against defects in materials and workmanship for a period of two (2) years from the date of shipment of the product. During the warranty period, Ultraview Corporation shall, at its option, either repair or replace hardware, software or firmware products which prove to be defective. This limited warranty does not cover damage caused by misuse or abuse by customer, and specifically excludes damage caused by the application of excessive voltages to the inputs and/or outputs of data acquisition boards.
While Ultraview Corporation hardware, software and firmware products are designed to function in a reliable manner, Ultraview Corporation does not warrant that the operation of the hardware, software or firmware will be uninterrupted or error free. Ultraview products are not intended to be used as critical components in life support systems, aircraft, military systems or other systems whose failure to perform can reasonably be expected to cause significant injury to humans. Ultraview expressly disclaims liability for loss of profits and other consequential damages caused by the failure of any product, and recommends that customer purchase spare units for applications in which the failure of any product would cause interruption of work or loss of profits, such as shipboard or military equipment.
THIS LIMITED WARRANTY IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED OR IMPLIED. THE WARRANTIES PROVIDED HEREIN ARE BUYER’S SOLE REMEDIES. IN NO EVENT SHALL ULTRAVIEW CORPORATION BE LIABLE FOR DIRECT, SPECIAL, INDIRECT, INCIDENTAL OR CONSEQUENTIAL DAMAGES SUFFERED OR INCURRED AS A RESULT OF THE USE OF, OR INABILITY TO USE THESE PRODUCTS. THIS LIMITATION OF LIABILITY REMAINS IN FORCE EVEN IF ULTRAVIEW CORPORATION IS INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.
Some states do not allow the exclusion or limitation of incidental or consequential damages, so the above limitation and exclusion may not apply to you. This warranty gives you specific legal rights, and you may also have other rights which vary from state to state.
Model Descriptions
The ULTRAD series of data acquisition and control boards are complete high-speed data acquisition and control systems on a single PCIBus card. These boards are designed for high speed, low jitter operation for scientific, medical, and industrial applications and function in PCIBus systems using the supplied drivers for Windows NTTM or Windows 95TM, Solaris 2.6, 7 or 8 Sparc Platform EditionTM or Solaris 2.6/Intel Platform EditionTM.
In addition to the on-board A/D and D/A converters, all ULTRAD series boards utilize TTL I/O. Each board is equipped with eight parallel TTL Inputs which can acquire digital data at the same rate, and concurrent with, the A/D samples. As well, each board is equipped with four parallel TTL outputs which can provide a high speed stream of digital data vectors at the same rate, and concurrent with the D/A samples, plus three simple programmable TTL outputs. The high speed TTL I/O vectors are unique to the ULTRADs, and enable them to dynamically control scientific or industrial apparatus at the same time analog data is being acquired or outputted.
The ULTRAD series includes three base models described below. Each model can be configured with a custom I/O module to further tailor the ULTRAD board to a specific application.
1 MODEL ADDA1280DX
Model ADDA1280DX is the deluxe version, which contains two simultaneously sampling 12-bit A/D converters, two simultaneously updated 12-bit D/A converters, and a total of 1 million 32-bit words (4 Megabytes) of dual-ported shared memory. Two A/D channels or two D/A channels may be simultaneously converted at up to 40 Ms/s. Alternatively, two D/A channels and two A/D channels may all be updated simultaneously at up to 20 Ms/s. Sampling is controlled by a high-speed automatic timebase which is software settable in increments of 25ns. Hence conversion intervals of 25ns (40Ms/s on two simultaneous channels or 80Ms/s on 1 channel), 50ns, 75ns, 100ns, ...., up to 6.375 μs/sample, are software selectable.
2 MODEL ADDA1280SX
Model ADDA1280SX is similar to the above model, but has only one 12-bit A/D converter and one 12-bit D/A converter, and a total of 1 million 16-bit words (2 Megabytes) of dual-ported shared RAM. The A/D or the D/A converter each can operate alone at up to 40 Megasamples/sec, or the A/D and D/A can operate simultaneously at up to 20 Megasamples/sec.. The automatic timebase can be set in 25ns steps, just as for the ADDA1280DX.
3 MODEL AD1280DX
Model AD1280DX is similar to the ADDA1280DX, but does not have any D/A converters. It includes dual, simultaneously sampled 12-bit A/D converters that can each sample at up to 40 Megasamples per second into a dual ported 1-million longword (4 Megabyte) RAM. The timebase can be set in increments of 25 ns, just as for the other models.
4 MODEL DA1280Dx
Model DA1280DX is similar to the ADDA1280DX, but does not have any A/D converters. It includes dual, simultaneously updated 12-bit D/A converters with up to 40 Megasamples per second each from its dual-ported 1-million longword (4 Megabyte) Ram. The timebase can be set in increments of 25 ns just as for the other models.
Specifications
The following specifications cover the standard models of the Ultrad 1280 series. However, personality modules containing special purpose input and output circuitry, can be added to the Ultrad 1280 board to achieve performance requirements not specifically outlined below.
1 A/D Converters
Number of Input Channels:
ADxx1280DX Models: 2 channels, simultaneously sampled
ADxx1280SX Models: 1 channel
A/D converter resolution: 12 Bits
Signal-to-noise Ratio: 66 dB at 40MHz sampling rate, 68dB at all
slower sampling rates.
Analog input range: -3V to +3V
Input impedance: 600 ohms in parallel with 15pF
Input connectors: Two standard SMB r.f. connectors.
Memory Depth: 1 Megasamples for each A/D converter
Maximum Sampling Rate:
Without simultaneous CPU access
to on-board RAM during sampling: 40 Megasamples/sec. (80 Ms/s on DX models)
With simultaneous CPU access
to on-board RAM during sampling: 20 Megasamples/sec. (40 Ms/s on DX models)
Continuous storage to disk: 500,000 to 2 Megasamples/sec. (2-8MB/sec),
depending on disk system throughput
Sample-to-sample period: 12.5 ns (80 MHz) and
25 ns (40 MHz) to 6.375μs in 25 ns increments
2 D/A Converters
Number of Output Channels:
xxDA1280DX Models: Two, simultaneously updated
xxDA1280SX Models: One
D/A resolution: 12 Bits
Signal-to-noise Ratio: 70 dB min. at all update rates
Memory Depth: 1 Megasample for each D/A converter.
Maximum Sampling Rate:
Without simultaneous CPU access
to on-board RAM during sampling: 40 Megasamples/sec on both channels at once.
With simultaneous CPU access
to on-board RAM during sampling: 20 Megasamples/sec on both channels at once
Continuous playback from disk: 500,000 to 2 Megasamples/sec. (2-8MB/sec),
depending on disk system throughput
Output voltage range: -3V to +3V at up to 2 mA output current
3 High Speed Vectored TTL Inputs
Number of TTL Input lines: 8, Simultaneously sampled at A/D sample rate
Input threshold: Standard TTL (Vil < 0.8V, Vih > 2.0V
4 High Speed Vectored TTL Outputs
Number of TTL Output lines: 4, Simultaneously updated at D/A sample rate
Output levels: Standard TTL (Vol < 0.4V, Voh > 2.4V
5 Low Speed Software-Programmed TTL Outputs
Number of TTL Output lines: 3, CPU-writable output bits, updated
independently of A/D, D/A or other TTL lines.
Output levels: Standard TTL (Vol < 0.4V, Voh > 2.4V)
6 General
Operating Temperature Range: 0 to +55 Degrees Celsius
Storage Temperature Range: -25 to +85 Degrees Celsius
Power Requirements +5V +/-5% at 3.8 Amperes Average Maximum
7 Physical
The Ultrad 1280 series are implemented as full size PCI bus printed circuit boards. The figure below shows the locations of the analog and I/O connectors, and LED indicators.
Because the Ultrad1280 board is 12.25 inches long, it will need a full length slot inside the PC chassis. The board has a cutout on the bottom edge to clear many motherboard CPUs.
[pic]
Hardware Architecture
The Ultrad1280 series of boards are comprised of a digital section and an analog section. The digital section includes a large dual-ported memory (1M x 32bits for Models with DX suffix, and 1M x 16-bits for models with SX suffix) for both A/D input data and D/A output data, and five high speed programmable logic arrays which implement the bus interface and the proprietary hardware engine which performs all data transfers. The digital section includes a high speed PCI target interface with burst cycle capability, a time base generator and a time stamp generator.
The analog section is comprised of input level shifting circuitry and A/D converter(s) (models ADDA1280DX and SX, AD1280DX, and D/A converter(s) (models ADDA1280DX and SX, and DA1280DX).
1 Analog Inputs
The two Analog Inputs have SMB-type coaxial connectors and can accept analog data with a voltage range from -3volts to +3 volts. The data at the two inputs is sampled continuously at 40 MHz but stored at the sample storage rate specified using the Ultrad Control Register. Furthermore, sample storage may be started and stopped using the EVENT input. By having the A/D converters always sample near their maximum rate, maximum accuracy can be realized by the board, and the data will be free of transients and other conversion errors that occur in boards in which the A/D converter is started and stopped.
2 Analog Outputs
The two Analog Outputs have SMB-type coaxial connectors and provide analog data with a voltage range of -3 to + 3 volts. The Output Data Rate is the same as the sample storage rate.
3 I/O connector
Ultrad boards use a micro-D type 26-pin connector to connect optional control signals for the conversion process, as well as TTL I/O lines. An I/O connector panel boardlet is included with all models which brings the TTL inputs and outputs and the TRIGGER and EVENT inputs to female BNC jacks. The pinout for the 26-pin connector is shown in the table below. The function for each signal is outlined in the following sections.
Note: EXTREME CARE MUST BE TAKEN TO ENSURE THAT NO VOLTAGES GREATER THAN +/-5V ARE EVER CONNECTED TO ANY ANALOG INPUT, AND NO VOLTAGE OUTSIDE THE 0 TO +5V RANGE IS EVER APPLIED TO ANY OTHER LINE.
|Pin |Signal Name |Pin |Signal Name |
| | | | |
|1 |OSSTB |2 |Digital GND |
|3 |OSDAT |4 |Digital GND |
|5 |OSCLK |6 |Digital GND |
|7 |/Event |8 |Digital GND |
|9 |TTL_Out[3] |10 |Digital GND |
|11 |TTL_Out[2] |12 |TTL_Out[1] |
|13 |TTL_Out[0] |14 |Trigger |
|15 |Digital GND |16 |TTL_In[7] / Ext Clock |
|17 |TTL_In[6] |18 |Digital GND |
|19 |TTL_In[5] |20 |TTL_In[4] |
|21 |TTL_In[3] |22 |Digital GND |
|23 |TTL_In[2] |24 |TTL_In[1] |
|25 |TTL_In[0] |26 |Digital GND |
A 26-pin I/O cable and printed-circuit-board-mountable connector are supplied with your Ultrad data acquisition board. A bottom view of the I/O connector is shown below.
[pic]
1 Trigger Input Line
The Trigger signal (TTL compatible) is used to in conjunction with the TTL compatible Event signal to permit the data acquisition process to be controlled by an external device. Upon the assertion of Trigger, the Ultrad board will begin recording A/D samples, as well as outputting D/A samples if so configured. ( See also Software_Run bit in Ultrad Control Register. )
If left unconnected, which is the most common case, the Trigger signal input is held in the asserted state by a pull-up resistor. In this case, sampling will start as soon as the Software_Run bit is set in the software.
2 Event Input Line
The Event signal is used in conjunction with the Trigger signal to allow a condition external to the Ultrad board to start and stop storing data. Once A/D sampling has begun (using the Trigger signal or the Software_Run bit) it will continue at the configured rate while the Event signal is driven high. If the Event signal is driven low at any time during the acquisition process, sampling will continue for one sample, and then a time-stamp will be written into the next memory location, after which the storage of data will stop until Event is brought high again.
If left unconnected (the most common case), the Event input is held in the asserted state by a pull-up resistor. In this case, the board will continuously sample (after Trigger has been asserted) without any interruptions and without any timestamp data being written to the RAM buffer.
3 TTL_In[7..0] / External Clock
In addition to the Analog Inputs, all Ultrad series boards are equipped with eight TTL inputs. Each of the two Input Channels includes a 12-bit A/D sample and four additional TTL level inputs. These TTL samples are stored in the upper four bits of the 16-bit sample data word.
Input Channel 0 will place TTL_In[3..0] into bits AD[15..12] of the Channel 0 data word.
Input Channel 1 will place TTL_In[7..4] into bits AD[31..28] of the Channel 1 data word.
The line used for TTL_IN[7] may alternatively be used as an external clock. This is generally not necessary, as the internal clock is more stable and has lower jitter than an external clock which shares the control cable with various other signals. Nevertheless, if it is desired to use an external clock instead of the internal clock, remove the jumper from the internal clock (lower) position, and instead install it in the external clock (upper) position, as shown in the figure in section 3.7. The external clock must be a good low-impedance TTL signal, such as that produced by a 74F244 buffer, and it must be at twice (or 4x, 6x, 8x, etc) the desired sampling frequency. The external clock frequency must always be between 20 MHz and 60 MHz. This allows a sampling rate of 10MHz to 30MHz if the sample interval is programmed to 0x01. Slower rates may be achieved by setting the sample interval to a larger number. For example, a sample interval of 0x04 and an external clock frequency of 50MHz will result in a sampling rate of 12.5MHz. In general it is better not to use an external clock, but instead use the trigger or event inputs to selectively sample data.
Note:
If the Event signal is used, TTL-IN[7] may not be used, as bit AD[31] of the channel 1 data word is used to indicate whether the sample is timestamp information or data.
4 TTL_Out[3..0]
In addition to the Analog Outputs, Ultrad boards have four TTL output pins on the I/O connector for controlling external devices or providing additional stimulus signals. These data bits, provided at the I/O connector, are updated concurrently with the D/A data and were stored in the RAM with each D/A sample. For more details, see the Memory Data Representation section.
5 Miscellaneous programmed TTL outputs (RSSTB, RSCLK, RSDAT)
In addition to the vectored TTL Outputs TTL-Out[3..0], all Ultrad 1280 series boards are equipped with three general-purpose TTL output pins on the I/O connector for controlling external devices. These data bits simply convey to the three lines RSSTB, RSCLK, and RSDAT the data that was last written to the control register at bits 18, 17 and 16, respectively. These TTL outputs are completely independent of all other TTL, A/D or D/A operation.
When this trio of signals are used as a control interface for external circuitry, the OSSTB signal can be used as a Frame Sync Bit, the OSDAT signal can be used as a Serial Data Bit, and the OSCLK signal can be used as a Serial Clock to control external devices.
4 Front-End Mezzanine Board Interface Connections
Each Ultrad board can be equipped with a mezzanine module to allow special purpose I/O devices to be used with the basic configuration. Such mezzanines could include rf demodulators or other front ends. Please contact the factory regarding custom mezzanine board development.
A 2x30 pin double row header strip is provided for mezzanine connections. The connector carries 32 data bits and the necessary voltages, clock, and output enable signals to interface a wide variety of custom I/O devices. Appendix A describes this interface connector.
5 LED Indicators
The two LED indicators on the top edge of the Ultrad board can be used during system integration to monitor the status of the Ultrad board. The functions of the LEDs are outlined below.
1 Run LED
The RUN LED is used to indicate an actual A/D or D/A sample is occurring. For configurations which use an external trigger (supplied via the I/O connector), this LED can be used to indicate a successful trigger. The LED will appear brighter or dimmer with faster or slower sample rates.
2 RDY ( Ready ) LED
The RDY LED is illuminated when the Ultrad board has been armed and is ready to begin storing A/D conversions. If no external control signals are used, the RUN and RDY indicators will be illuminated simultaneously.
Low-level Software Interface
The Ultrad board is very easy to communicate with. In most cases, this section may be skipped, as the drivers supplied with the board automatically handle all communication with the board registers. The best way to develop your own custom software is simply to modify the appropriate sample programs included with the board, and then recompile. However, the following section gives an overview of how the driver calls actually control the board.
The software interface consists of a PCI type-00 Configuration Header, three board specific registers, including a Control Register, and a dual-ported, 4 Megabyte RAM (2 MB for SX models). Each of these groups of registers is outlined in the following sections.
Note:
All accesses the dual-ported RAM should be made as 32-bit (LONGWORD) transfers. Accesses to the CONTROL REGISTER should also be made as 32-bit transfers, but are automatically made by the driver, and are NOT DIRECTLY MADE BY THE USER PROGRAM.
1 PCI Configuration Header
The Ultrad series boards support an abbreviated PCI Configuration Header necessary for operation in a PCIBus environment. A map of the Ultrad PCI Configuration Header is shown below. Registers which are optional or not implemented on the Ultrad 1280 are left blank.
|Double Word Address |byte 3 |byte 2 |byte 1 |byte 0 |
|00 H |Device ID |Vendor ID |
|04 H |Status |Command |
|08 H |Class Code |Revision ID |
|0C H | |Header Type | | |
|10 H |Base Address for ULTRAD data memory |
|14 H | |
|18 H | |
|1C H | |
|20 H | |
|24 H | |
|28 H | |
|2C H | | |
|30 H | |
|34 H | |
|38 H | |
|3C H | | |Interrupt Pin |Interrupt Line |
The board control register is mapped at configuration space address 80H, as well as in memory space at Base Address + 1FFFFFC. Accessing either place will read or write this register.
|Double Word Address |byte 3 |byte 2 |byte 1 |byte 0 |
|80 H |Ultrad Control Register |
2 Ultrad Control Register
The Ultrad Control Register is used to configure the Ultrad board before operation and can be used to start and stop the data acquisition process. This register should not be confused with the Command register in the PCI Configuration Header. The following table shows the positions of the bits in the Ultrad Control Register. The functions of each of the bits in the Ultrad Control Register are outlined in the sections which follow. The first table shows the function of the Control register during a write. Note that during a read, these bits will not be read back, but instead, two of the bit positions may be read, as shown in the second table. Note that the bits in the control register are not directly written nor read by user programs, but are modified by calls to the drivers, which are each summarized in the discussion of the respective bit.
|Bit |Function |
| | |
|27 |Software_Run |
|26 |Buffer_Wrap |
|24 |/Interrupt_Enable |
|21 |Double_Speed |
|20 |AD_DA |
|18 |RSSTB |
|17 |RSCLK |
|16 |RSDAT |
|15 |TimeStamp_Test |
|7..0 |Sample_Interval [7..0] |
Function of Control Register bits during write.
|Bit |Function |
| | |
|29 |Board Interrupting |
|28 |Board Stopped |
| | |
Function of Control Register bits during read.
1 Software_Run (write only)
Software_Run is used to start and stop the data acquisition process. If no connection to external control signals is made through the I/O connector (Trigger and Event ) then data acquisition begins when Software_Run is set to 1, and ends when it is set to 0. If the external control signals are used, Software_Run must be set to 1 before Trigger can initiate data acquisition. As well, acquisition will stop when Software_Run is set to 0.
The Software_Run bit is automatically set to 1, turning on the board, using the start_ultrad_io() driver call under Windows NT or 95/98 or the ultrad_set_go() call under the Solaris (UNIX) OS.
The Software_Run bit is automatically set to 0, stopping the board, using the end_ultrad_io() driver call under Windows NT or 95/98or the ultrad_stop() (or indirectly by the ultrad_stop_at_n_blocks() calls under the Solaris operating system.
2 Buffer_Wrap (write only)
Buffer_Wrap is used to specify if the RAM buffer will be filled with A/D conversion samples a single time (storage stops when memory is filled) or if it will be treated as a cyclic buffer and filled continuously, wrapping around to the start of the buffer after the end is reached.
When set to 0, the Buffer_Wrap control bit will cause data acquisition to end when the RAM buffer has been filled once completely.
When Buffer_Wrap is set to 1, A/D data will be stored to RAM continuously. When the buffer has been filled, the next A/D sample will be stored in the first RAM data location and the buffer will be overwritten with new data.
The Buffer_Wrap bit is automatically set to 1, enabling the wraparound mode, using the setup_ultrad_io(..,ULTRAD_FILE_IO) driver call under Windows NT or 95/98 or the ultrad_set_wrap() call under the Solaris operating system.
The Buffer_Wrap bit is automatically set to 0, disabling the wraparound mode, using the setup_ultrad_io(.., ULTRAD_INTERACTIVE_IO) driver call under Windows NT or 95 or the ultrad_unset_wrap( ) call under the Solaris operating system.
3 Interrupt_Enable (write only)
The Interrupt_Enable bit enables the Ultrad to issue interrupts as its RAM buffer is filled. Once acquisition begins and A/D samples are written to this buffer, the Ultrad issues an interrupt as each eighth of the buffer is filled. If Interrupt_Enable is set to 0, interrupts will be generated. If set to 1, interrupts will not be generated.
The Interrupt_Enable bit is automatically set to 0, enabling interrupts, any time the board is started under Windows NT or 95/98 or by using ultrad_set_int() under the Solaris OS.
The Interrupt_Enable bit is automatically set to 1, disabling interrupts, when the board is stopped under Windows NT or 95/98or by using the ultrad_unset_int( ) call under the Solaris OS.
4 Double_Speed (write only)
The Double_Speed bit is used to allow the Ultrad board to perform data acquisition at 80 MHz on a single channel (ADDA1280DX or AD1280DX Models only – not on ADDA1280SX models).
When Double_Speed is set to 0, the two A/D converters will perform data conversion simultaneously. This is the normal mode of operation, and the maximum sample rate in this mode is 40 MHz on the two A/D channels simultaneously.
When Double_Speed is set to 1, the two A/D converters will perform sequential data conversions. This mode is used to perform A/D conversions at 80 MHz, assuming SAMPINT is set to 0. In this mode, only Analog Input 0 is sampled, and Analog Input 1 is ignored.
5 AD_DA (write only)
AD_DA is used to select D/A operation in addition to A/D operation.
When set to 0, the Ultrad performs only A/D sampling, at any specified sample rate, up to 40Ms/s.
When set to 1, the Ultrad will perform both A/D and D/A conversions concurrently, at any specified sample rate up to 20 Ms/s. If AD_DA is set to one, and a sample rate of 40MS/s is specified (sample interval=0x01), the D/A (only) will convert at 40Ms/s, but no A/D conversions will occur.
This bit should also be set to 1 if D/A-only operation is desired. If a sample interval of 0x01 was specified, no A/D conversion will simultaneously take place. If slower sample rates (sample intervals of 0x02 or more) are specified, A/D conversions will also take place, concurrently, but these should cause no problems, since the A/D data that appears in each memory location (after the D/A conversion was made) may simply be ignored.
The AD_DA bit is automatically set to 1, enabling concurrent A/D and D/A operation, using the setup_ultrad_io(ULTRAD_WRITING TO BOARD,..) driver call under Windows NT or 95 or the ultrad_set_adda_mode() call under the Solaris operating system.
The AD_DA bit is automatically set to 0, disabling D/A operation, using the setup_ultrad_io(ULTRAD_READING_FROM_BOARD,..) driver call under Windows NT or 95 or the ultrad_unset_adda_mode( ) call under the Solaris operating system.
6 RSSTB (write only)
The RSSTB, RSDAT, and RSCLK bits are intended to be used together to provide a serial communication path for control of devices connected to the Ultrad board.
RSSTB is a registered control bit connected to the OSSTB pin on the I/O connector. It can be used as a Frame Sync bit for control of devices connected to the Ultrad board, or alternatively can be used as a general write-only TTL output bit.
The RSSTB bit is automatically set to 1, driving the OSSTB output to a TTL logic 1, using the set_ultrad_board_register(ultrad_board_handle,ULTRAD_RSSTB, TRUE) driver call under Windows NT or 95/98 or the ultrad_set_serial() call under the Solaris operating system.
The RSSTB bit is automatically set to 0, driving the OSSTB output to a TTL logic 0, using the set_ultrad_board_register(ultrad_board_handle, ULTRAD_RSSTB,FALSE) driver call under Windows NT or 95/98 or the ultrad_set_serial( ) call under the Solaris operating system.
7 RSCLK (write only)
RSCLK is a registered control bit connected to the OSCLK pin on the I/O connector. It can be used as a Data Clock for control of devices connected to the Ultrad, or alternatively can be used as a general write-only TTL output bit.
The RSCLK bit is automatically set to 1, driving the OSCLK output to a TTL logic 1, using the set_ultrad_board_register(ultrad_board_handle,ULTRAD_RSCLK, TRUE) driver call under Windows NT or 95/98 or the ultrad_set_serial() call under the Solaris operating system.
The RSCLK bit is automatically set to 0, driving the OSCLK output to a TTL logic 0, using the set_ultrad_board_register(ultrad_board_handle, ULTRAD_RSCLK,FALSE) driver call under Windows NT or 95/98 or the ultrad_set_serial( ) call under the Solaris operating system.
8 RSDAT (write only)
RSDAT is a registered control bit connected to the OSDAT pin on the I/O connector. It can be used as a Serial Data bit for control of devices connected to the Ultrad board, or alternatively can be used as a general write-only TTL output bit.
The RSDAT bit is automatically set to 1, driving the OSDAT output to a TTL logic 1, using the set_ultrad_board_register(ultrad_board_handle,ULTRAD_RSDAT, TRUE) driver call under Windows NT or 95/98 or the ultrad_set_serial() call under the Solaris operating system.
The RSDAT bit is automatically set to 0, driving the OSDAT output to a TTL logic 0, using the set_ultrad_board_register(ultrad_board_handle, ULTRAD_RSDAT,FALSE) driver call under Windows NT or 95/98 or the ultrad_set_serial( ) call under the Solaris operating system
9 TimeStamp_Test (write only)
This bit is a Built-In-Self-Test for factory use during testing. Users should not set this bit to 1.
10 Sample Interval (write only)
The Sample_Interval word determines the A/D and D/A conversion rate. The value written to Sample_Interval[7..0] specifies the number of 25ns periods between samples. A partial table of Sample_Interval values and conversion periods and frequencies is below. Note that sampling rates slower than 156.8Khz may be realized by setting the board to one of the lowest sampling rates, and then merely skipping alternate samples when reading the A/D data from RAM (and duplicating the same sample several times in RAM when writing data for output via the D/As). For example, a sample rate of 10KHz may be attained by setting the board for 100KHz sampling, and incrementing the pointer by 10 each time an A/D sample is read from RAM. Any D/A data would be written into 10 successive locations for each sample to accomplish this slow sampling.
Note: Simultaneous CPU access is not supported at sample rates of 20 MHz and above,
|Sample_Interval[7..0] |Conversion Period |Conversion Frequency |
|( decimal ) | | |
| | | |
|1 | | |
|(with Double_Speed) |12.5 ns |80.0000 MHz |
|1 |25.0 ns |40.0000 MHz |
|2 |50.0 ns |20.0000 MHz |
|3 |75.0 ns |13.3333 MHz |
|. . . |. . . |. . . |
|254 |6.350 us |157.480 kHz |
|255 |6.375 us |156.863 kHz |
To determine the sampling period more generally, use the following equation.
Frequency = 1 / ( Sample_Interval ) x 25 ns
The Sample interval is set using the set_ultrad_board_register(board_handle, ULTRAD_SAMPLE_RATE, (USHORT) board_speed) driver call under Windows NT or 95/98 or the ultrad_set_sampint() call under the Solaris operating system.
11 Board Interrupting (read only status bit)
This bit (bit 29), when 1, indicates that the Ultrad has issued an interrupt that is pending. This bit is automatically cleared by any write to the board’s control register. It should be checked every time the interrupt service routine for this driver is entered, to be sure that it was the Ultrad that actually issued the interrupt presently being serviced.
12 Board Stopped (read only status bit)
This bit (bit 28), indicates whether the Ultrad1280 has stopped, in the case where the Wrap bit is not set, and the board has finished an acquiring an entire board full of data. This bit is a 1 in this case, and is a 0 in all other cases, including when the board is stopped due to the Run bit being set to 0. It’s function is superfluous, as the driver will alternately know that the board has finished acquiring a board full of data by the fact that eight interrupts have been received from the board.
3 Data Representation in Memory
The RAM buffer can hold data for D/A conversion, stored A/D samples, or both. The data to be converted to an analog waveform can be placed in the RAM buffer and clocked out to the D/A converters. Then, A/D conversion data can be written to a RAM buffer address immediately after the D/A data has been read out. The arrangements of data for each case are outlined below. Note: The shaded areas are used for ‘DX models only. On the ADDA1280SX model, these bit fields do not contain valid data, and must be ignored or masked out by your software.
Each double longword of RAM can contain two D/A values and the associated TTL values. Once conversion is started, two D/A values are sent to the D/A converters on each RAM read cycle. The format below is also identical to the format in which data is stored to disk in the example programs in all Ultraview-supplied software packages.
|Address |D31 |D30 - D28 |D27 - D16: D/A Data for |D15 - D12 |D11 - D0: D/A Data for |
| | | |Chan 0 | |Chan 1 |
| | | |(DX MODELS ONLY) | | |
|BA+$0000000 |x |x |Chan 0 Samp 0 |TTLOut[3.0] |Chan 1 Samp 0 |
|BA+$0000004 |x |x |Chan 0 Samp 1 |TTLOut[3.0] |Chan 1 Samp 1 |
|BA+$0000008 |x |x |Chan 0 Samp 2 |TTLOut[3.0] |Chan 1 Samp 2 |
|BA+$000000C |x |x |Chan 0 Samp 3 |TTLOut[3.0] |Chan 1 Samp 3 |
|BA+$0000010 |x |x |Chan 0 Samp 4 |TTLOut[3.0] |Chan 1 Samp 4 |
|BA+$0000014 |x |x |Chan 0 Samp 5 |TTLOut[3.0] |Chan 1 Samp 5 |
|BA+$0000018 |x |x |Chan 0 Samp 6 |TTLOut[3..0] |Chan 1 Samp 6 |
|BA+$000001C |x |x |Chan 0 Samp 7 |TTLOut[3..0] |Chan 1 Samp 7 |
|. |x |x |. | | |
|. |x |x | | | |
|BA+$003FFFFF |x |x |Chan 0 Sample 1048576 |TTLOut[3..0] |Chan 1 Sample 1048576 |
The data from the A/D converter is in offset binary format. Because of the dynamic range of the data converters, the largest digital number corresponds to +3 volts, and the smallest digital number corresponds to -3 volts.
|Digital Value |Analog Value |
| | |
|1111 1111 1111 |+3 volts. |
|1000 0000 0000 |0 volts |
|0000 0000 0000 |-3 volts |
The following table illustrates the arrangement of A/D data samples stored in the RAM buffer. The first two A/D samples are stored on the same RAM write cycle and appear in the same 32-bit long word. The upper four bits of each longword contain the TTL sample bits. The memory address for each sample is shown in the address column. Bit 31 is used to distinguish Time Stamp values from A/D conversion data. Note: The shaded areas below are used for ‘DX models only. On the ADDA1280SX model, these bit fields do not contain valid data, and must be ignored or masked out by your software.
The Event column shows the relationship of the Event signal ( if used ) to the stored data. The first row of the table shows the Event signal driven high and the resulting storage of conversion data. Two samples are stored on each 32-bit RAM write cycle. Row three shows the Event signal being driven low. Conversion data storage begins immediately after Event is driven high, but continues for one dual sample after Event is driven low. The table shows the next sample stored to memory followed by the Time Stamp value.
The resumption of data storage can begin as soon as Event is again driven high and will continue as long as the appropriate control bits ( Event, Software_Run ) are asserted. A Time Stamp value is placed in memory after each series of conversion samples.
|Address |D31 |D30 - D28 |D27 - D16: A/D Chan |D15 - D12 |D11 - D0 A/D Chan 1 |Event |
| | | |0 Data (Not present on| |Data | |
| | | |SX models) | | | |
| | | | | | | |
|BA+$0000000 |0 |TTL_In[6..4] |A/D samp 0 |TTL_In[3..0] |A/D samp 0 |1 |
|BA+$0000004 |0 |TTL_In[6..4] |A/D samp 1 |TTL_In[3..0] |A/D samp 1 |1 |
|BA+$0000008 |0 |TTL_In[6..4] |A/D samp 2 |TTL_In[3..0] |A/D samp 2 |1 |
|BA+$000000C |0 |TTL_In[6..4] |A/D samp 3 |TTL_In[3..0] |A/D samp 3 |1 |
|BA+$0000010 |0 |TTL_In[6..4] |A/D samp 4 |TTL_In[3..0] |A/D samp 4 |1 |
|BA+$0000014 |0 |TTL_In[6..4] |A/D samp 5 |TTL_In[3..0] |A/D samp 5 |1 |
|BA+$0000018 |0 |TTL_In[6..4] |A/D samp 6 |TTL_In[3..0] |A/D samp 6 |1 |
|BA+$000001C |0 |TTL_In[6..4] |A/D samp 7 |TTL_In[3..0] |A/D samp 7 |1 |
|BA+$0000020 |0 |TTL_In[6..4] |A/D samp 8 |TTL_In[3..0] |A/D samp 8 |1 |
|BA+$0000024 |0 |TTL_In[6..4] |A/D samp 9 |TTL_In[3..0] |A/D samp 9 |1 |
|BA+$0000028 |0 |TTL_In[6..4] |A/D samp 10 |TTL_In[3..0] |A/D samp 10 |0 |
|BA+$000002C |1 |31-bit Time Stamp Value |
|BA+$0000030 |0 |TTL_In[6..4] |A/D samp 11 |TTL_In[3..0] |A/D samp 11 |1 |
|BA+$0000034 |0 |TTL_In[6..4] |A/D samp 12 |TTL_In[3..0] |A/D samp 12 |1 |
|. |. |. |. |. |. |. |
4 Time Stamp Function
All Ultrad series boards are equipped with a Time Stamp Counter to record the relative time positions of discontinuous A/D converter samples. The 31-bit counter has a resolution of 100 ns and can record intervals up to 214.7 seconds. The Time Stamp may be used for A/D-only sampling, or for the A/D portion of A/D+D/A sampling. In the latter case, both the A/D conversions and the D/A conversions will simultaneously stop when Event is brought low, and will resume when Event is again brought high.
In normal operation, the Time Stamp counter is started when the first A/D sample is written to RAM and will run continuously and wrap automatically until Event or Software_Run is deasserted. When sampling is suspended or stopped, the 31-bit Time Stamp value is written to RAM. Data bit 31 is set to 1 to indicate the recorded value is a time stamp value and not A/D data.
Typical applications include reflected wave measurements, radar, and NMR development, or any application which requires recording only certain portions of an analog waveform.
If the EVENT / Timestamp capability is used, TTL Input 7 may not be used to record TTL input data, and as a result the ULTRAD only has 7 usable TTL input lines when EVENT/Timestamp is used. If timestamping is used, you must tie TTL Input 7 to ground, which can be conveniently done by jumpering the I7 signal on the I/O Connector Panel to ground. If TTL Input 7 is not tied to ground, then it may float high, in which case there will be data samples in which bit 31 is a 1, which will make it impossible for your software to determine whether the data word is a sample or a timestamp word.
Hardware Installation and Setup
1 PCIBus Installation
Before you begin, clear an area around the computer system, leaving plenty of room to work.
1. Use the shutdown command on your PC or workstation and then turn OFF the power to the computer. Disconnect the power cord.
WARNING:
BEFORE REMOVING THE COMPUTER SYSTEM COVER OR REMOVING ANY BOARD, BE SURE THAT THE POWER TO THE COMPUTER, AS WELL AS TO ALL PERIPHERAL DEVICES IS OFF. WEAR A STATIC-DISSIPATING WRISTBAND WHICH IS GROUNDED TO THE SYSTEM CHASSIS WHILE OPENING OR WORKING ON YOUR SYSTEM.
2. Remove any screws that attach the computer system cover and remove the cover.
3. Remove the filler bracket from the PCIBus slot into which you wish to install your Ultrad board. For more details, refer to the hardware manual for your computer system.
4. Hold the ULTRAD board by the top of the metal PCI bracket. Then carefully hook the tab on the bottom edge of the Ultrad's metal bracket into the corresponding slot in the computer's rear panel. Carefully push the Ultrad down so its PCIBus connector mates with the PCIBus connector on the system's motherboard. Press down on the plastic handle gently to make sure that the Ultrad is seated firmly into the PCIBus connector on the motherboard.
Check to be sure that no other PCI boards have become unseated when the ULTRAD was installed, as it is common for PC motherboards to flex slightly when installing PCI boards.
5. Plug the coaxial I/O cables for the analog inputs and/or outputs into the appropriate SMB connectors on the Ultrad's rear bracket at the rear of the system. You should not plug in the 26-conductor I/O cable unless you will be using the Trigger line, Event line or any of the TTL I/O lines. Connect the free ends of the analog I/O cables to the signal sources to be digitized.
6. We recommend that channels 0 (and 1 if using a 'DX model) initially be connected to a signal generator set for a 2 volt peak sine wave at approximately 10 kilohertz. This will allow a quick initial test of the Ultrad's functionality using the demonstration software supplied with the board.
6. Replace the computer system cover, installing all screws you had removed. Reconnect the power cables to the system and peripherals.
7. Power up and reboot the system. The system will then be ready for software installation.
2 Software Installation for Windows 2000 or Windows NT TM
Before installing the software, be sure the board is installed in the system. Then, insert the diskette titled ULTRAD-1280 DRIVER PKG WITH USER DEMO SOFTWARE - FOR WinNT TM and Win95/98. Create a directory for installing the ULTRAD software, as follows:
C:> mkdir ultrad
Then, copy the entire contents of the diskette to the new directory as follows:
C:> xcopy a: C:\ultrad /s /e /v
To run the software, please refer to the document Quick Setup for ADDA1280 Under Win95,98TM or NTTM
3 Software Installation for Windows 95TM, 98 or Windows METM
Before installing the software, be sure the board is installed in the system. Then, insert the diskette titled ULTRAD-1280 DRIVER PKG WITH USER DEMO SOFTWARE - FOR WinNT and Win95/98/ME TM. Create a directory for installing the ULTRAD software, as follows:
C:> mkdir ultrad
Then, copy the entire contents of the diskette to the new directory as follows:
C:> xcopy a: C:/ultrad /s /e /v
To run the software, refer to the manual Quick Setup for ADDA1280 Under Win95/98TM or NTTM.
If you have trouble running the ADDA1280 in some systems with Plug-and-Play (PNP) BIOS, shut down your system, go into the initial bios setup menu, and disable the plug-and-play option. Then reboot the system, and retry running the ADDA1280 software which should now run.
4 Software Installation for Solaris 2.6,7,8 (Sparc Platform Edition)TM
Before installing the software, be sure the board is installed in the system. Then, insert the diskette titled ULTRAD-1280 DRIVER PKG WITH USER-DEMO SOFTWARE-FOR SOLARIS 2.7 SPARC PLATFORM.
Log in as root, and type in the following two lines at the prompt (shown here as #):
# volcheck
# pkgadd -a none -d /floppy/floppy0/uvpci
You will be shown a list of packages on the diskette (should be Ultrad only) and asked which you wish to install. You can just take the default (press Return) to install the package.
Next, the installation script will ask you which directory should be the base directory for the package. You can choose /opt/uvpci, or choose some other place on your system. You should choose an empty directory for installation; extra files or directories might cause problems.
The pkgadd program may issue a warning about /etc/devlink.tab; ignore the warning, as it is just going to modify the file, not overwrite it.
You may also see a question about running programs with superuser permissions – you should just answer yes to this.
Once all the files have been copied to the base directory, some installation scripts are automatically run, giving a usable binary distribution of the package.
One of the questions you are asked by the post-installation script is whether you wish to recompile the package. If you have the Gnu C compiler (this compiler is free from Gnu and is the recommended compiler for developing software for the Ultrad boards) or the SunPro C compiler, you can recompile. You will be asked where the compiler resides (eg. /opt/gnu/bin/).
Just before returning to the prompt, pkgadd will warn you that you need to reboot your system. This is because a new driver has been added to the system. Do the following:
# /usr/bin/shutdown -y -i6 -g0
When the system reboots, the driver will be installed and operational. Go to the directory bw_dig_osc, to run a combined oscilloscope/signal generator demo. Connect a signal generator set for a 2 volt peak signal at 10 kilohertz to both A/D input channels. Also, if your ULTRAD has D/A converters, connect the two D/A outputs to an oscilloscope set for 1V/Div and 20 μs per division. Each time you click on the “Digitize” button on the screen, the ULTRAD board should digitize and display on the computer screen the data from the signal generator. It should also output a triangle and a sine wave on its D/A channels which should be seen on your oscilloscope.
You may next want to go to the example_programs directory, and run some of the examples, such as acquire_data, which stores A/D data to disk, or da_from_disk, which plays back disk data on the optional D/A converters. Another example, synth, outputs two continuous CPU-generated sine waves. The example adthenda reads in data continuously via the A/D converters, and then slightly modifies this data and continuously outputs the modified data via the D/As.
The above example programs are clearly commented, and are a good starting point for users who are developing their own code. They can easily be modified and recompiled by suitably modifying the makefile and then typing “make”.
For a more in depth discussion of the software, please refer to the document Programming the Ultrad Board under Solaris OS.
In case of trouble recompiling the software in the bw_dig_osc directory under Solaris 8, it may be necessary to modify (edit) the file “Makefile” in the bw_dig_osc directory, by doing the following:
Change the line “FLAGS=-g” to “FLAGS=-g -D OWTOOLKIT_WARNING_DISABLED”
After this change is made to the makefile, then recompile, by typing “make”.
5 Software Installation for Solaris 2.6 (Intel Platform)TM
Insert the diskette titled ULTRAD-1280 DRIVER PKG WITH USER-DEMO SOFTWARE-FOR SOLARIS-INTEL PLATFORM. The installation and use of this package is otherwise identical to that of the Solaris86 Sparc Platform edition.
Windows and Windows NT are trademarks of Microsoft Corp TM.
APPENDIX A. FRONT-END MEZZANINE BOARD INTERFACE
The ULTRAD1280 board is available in two main configurations:
1) The standard configuration ADDA1280/AD1280/DA1280 boards, which have A/D and optional D/A converters installed on the board, and do not therefore need a front-end-pod interface, since the front-end is already installed on the main PCI board.
2) The ULTRAD1280CAR board, which has a connector P3, which is the Front-end Mezzanine Interface. This interface allows various mezzanine boards to be installed on the ULTRAD1280CAR board for implementing custom front-end options or standard options, such as the ULTTL1280 parallel TTL I/O interface. These front-end options are in lieu of the standard 12-bit A/D and D/A converters that are normally configured with the ULTRAD1280. In some cases OEM customers may design mezzanine boards of their own which will mount on the ULTRAD1280CAR, and thereby implement a custom function.
1 Front-end Mezzanine Interface Pinout
The following is the pinout of connector P3, as viewed from the front (component side) of the ULTRAD1280 board: Outputs from the ULTRAD1280 are shown as (O), inputs are shown as (I).
-----------------------
PIN
2 GROUND
4 ADCNT (O)
6 GROUND
8 GROUND
10 GROUND
12 DD30 (I/O)
14 DD28 (I/O)
16 DD26 (I/O)
18 DD24 (I/O)
20 GROUND
22 DD22 (I/O)
24 DD20 (I/O)
26 DD18 (I/O)
28 DD16 (I/O)
30 GROUND
32 DD14 (I/O)
34 DD12 (I/O)
36 DD10 I(/O)
38 DD08 (I/O)
40 GROUND
42 DD06 (I/O)
44 DD04 (I/O)
46 DD02 (I/O)
48 DD00 (I/O)
50 TRIGGER (I/O)
52 GROUND
54 RSDAT (O)
56 GROUND
58 BO0 (O)
60 AD12LE1 (O)
PIN:
NOT USED 1
/PBOE (O) 3
NOT USED 5
/DA (O) 7
MCLK (O) 9
DD31 (I/O) 11
DD29 (I/O) 13
DD27 (I/O) 15
DD25 (I/O) 17
-5.5V @ 100mA (O) 19
DD23 (I/O) 21
DD21 (I/O) 23
DD19 (I/O) 25
DD17 (I/O) 27
-5.5V @ 100mA (O) 29
DD15 (I/O) 31
DD13 (I/O) 33
DD11 (I/O) 35
DD09 (I/O) 37
+5.5V @ 250mA (O) 39
DD07 (I/O) 41
DD05(I/O) 43
DD03 (I/O) 45
DD01 (I/O) 47
+5.5V@250mA (O) 49
NOT USED (RESV’d) 51
RSSTB (O) 53
RSCLK (O) 55
NOT USED 57
AD12LE0 (O) 59
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