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BEARYS INSTITUTE OF TECHNOLOGYMANGALOREDEPARTMENT OF ELECTRONICS AND COMMUNICATIONHARDWARE DESCRIPTION LANGUAGE (HDL)LAB MANUALSUB CODE: 10ECL48 2013INDEXPART A(Simulation and Interfacing)Sl.NoName of the experiment1HDL code for all the gates2HDL codes for the combinational designa. 2 to 4 decoderb.(i) 8 to 3 encoder without priority b.(ii) 8 to 3 encoder with priorityc. 8 to 1 multiplexerd. (i) 4 bit binary to gray converter d.(ii) 4 bit gray to binary convertere. 4 to 1 Multiplexer f. Comparator.3HDL code for N-bit ALU4HDL code to describe the functions of a Full Adder Using three modeling stylesData flow modelingBehavioral ModelingStructural modeling5HDL code for the following flip-flopsSR flipflopD flipflop JK flipflop T flipflop6HDL code for (i)4 bit binary counter with synchronous reset(ii)4 bit counter with asynchronous reset(iii) BCD counter PART BINTERFACINGSl.NoName of the experiment1HDL code to display messages on the given seven segment displayand LCD and accepting Hex key pad input data.2HDL code to control speed, direction of DC motor.3HDL code to control speed, direction of Stepper motor.4HDL code to generate different waveforms using DAC change the frequency and amplitude.Square waveTriangular waveRamp waveSawtooth wavePART AOUTPUT 1Program1. Write VHDL code to realize all gateslibrary IEEE;use IEEE.STD_Logic_1164.ALL;use IEEE.STD_Logic_ARITH . ALL;use IEEE.STD_Logic_UNSIGNED.ALL;entity gates is Port (Ain :in std_logic; Bin :in std_logic;Op_not : out std_logic;Op_or : out std_logic;Op_and :out std_logic;Op_nor :out std_logic;Op_nand : out std_logic;Op_xor : out std_logic;Op_xnor: out std_logic);end gates;architecture Behavioral of gates isbegin Op_not<= not Ain; Op_or <= Ain or Bin; Op_and <= Ain and Bin; Op_nor <= Ain nor Bin; Op_nand <= Ain nand Bin; Op_xor <= Ain xor Bin; Op_xnor <= Ain xnor Bin;end Behavioral;Write verilog code to realize all gatesmodule allgates(A,B,not1, or2,and3, nor4,nand5,xor6, xnor7); input A; input B; output not1; output or2; output and3; output nor4; output nand5; output xor6; output xnor7; reg not1; reg or2; reg and3; reg nor4; reg nand5; reg xor6; reg xnor7; always@(A or B) beginnot1 = ~(A);and3 = (A) & (B); or2 = A|B; nand5= ~((A) & (B)); nor4= ~((A) | (B)); xor6= (A) ^ (B);xnor7= ~((A) ^ (B));endendmoduleOUTPUT 2.aProgram 2.a Write VHDL code for 2 to 4 decoderlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity Decoder2_4 isport(Enable: in STD_LOGIC;D_IN: in STD_LOGIC_VECTOR(1downto 0);D_OUT: out STD_LOGIC_VECTOR(3 downto 0));end decoder2_4;architecture Decoder_arc of Decoder2_4 isbeginprocess (Enable,D_IN)beginif (Enable='1')thenD_OUT<="0000";elsecase D_IN iswhen "00"=>D_OUT<="0001";when "01"=>D_OUT<="0010";when "10"=>D_OUT<="0100";when "11"=>D_OUT<="1000";when others=>NULL;end case;end if;end process;end Decoder_arc;Write verilog code for 2 to 4 decodermodule decoder(a, en,y);input[1:0]a;input en;output[3:0]y;reg[3:0]y;always@(en or a)beginif(en= =1)y=4'b0001;elsecase(a)2'b00:y =4'b0001;2'b01:y= 4'b0010;2'b10:y= 4'b0100;2'b11:y= 4'b1000;default :y=4'b0000;endcaseendendmoduleOUTPUT 2.b(i)Program 2.b(i) Write VHDL code for 8 to 3 encoder without prioritylibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;entity code isport(EN:in STD_LOGIC;D_IN: in STD_LOGIC_VECTOR(7 downto 0);D_OUT: out STD_LOGIC_VECTOR(2 downto 0));end code;architecture encoder_arch of code is beginprocess(EN,D_IN)beginif (EN='1')thenD_OUT<="000";elsecase D_IN iswhen "00000001"=>D_OUT<="000";when "00000010"=>D_OUT<="001";when "00000100"=>D_OUT<="010";when "00001000"=>D_OUT<="011";when "00010000"=>D_OUT<="100";when "00100000"=>D_OUT<="101";When "01000000"=>D_OUT<="110";when "10000000"=>D_OUT<="111";when others=>NULL;end case;end if;end process;end encoder_arch;Write verilog code for 8 to 3 encoder without prioritymodule encode(Ain, En,Yout);input En;input [7:0]Ain;output[2:0]Yout;reg [2:0]Yout;always @ (En or Ain)beginif (en==1)Yout=3'b0;elsecase (Ain)8'b00000001:Yout=3'b000;8'b00000010:Yout=3'b001;8'b00000100:Yout=3'b010;8'b00001000:Yout=3'b011;8'b00010000:Yout=3'b100;8'b00100000:Yout=3'b101;8'b01000000:Yout=3'b110;8'b10000000:Yout=3'b111;default:Yout=3'b000;endcaseendendmodule OUTPUT 2.b(ii)Program 2.b(ii) Write VHDL code for 8 to 3 encoder with prioritylibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity prio isPort (e :in std_logic;din :in std_logic_vector(7 downto 0);dout : out std_logic_vector(2 downto 0));end prio;architecture Behavioral of prio isbeginprocess(din,e)beginif(e='1')thendout<="000";elsif(din(0)='1')thendout<="000";elsif(din(1)='1')thendout<="001";elsif(din(2)='1')thendout<="010";elsif(din(3)='1')thendout<="011";elsif(din(4)='1')thendout<="100";elsif(din(5)='1')thendout<="101";elsif(din(6)='1')thendout<="110";else dout<="111";end if;end process;end Behavioral;Write verilog code for 8 to 3 encoder with prioritymodule prienco1(e,din,dout); input[7:0]din; input e;output[2:0]dout; reg[2:0]dout; always@(din,e) begin if (e= =1) dout=3'b000; else if (din[0]==1)dout=3'b000; else if(din[1]==1)dout=3'b001; else if(din[2]==1)dout=3'b010; else if(din[3]==1)dout=3'b011; else if(din[4]==1)dout=3'b100; else if(din[5]==1)dout=3'b101; else if(din[6]==1)dout=3'b110; else if(din[7]==1)dout=3'b111; else dout=3'b000; end endmoduleOUTPUT 2.cProgram 2.cWrite VHDL code for 8 to 1 multiplexerlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALLentity Mux8_1 isport(SEL:in STD_LOGIC_VECTOR(2 downto 0);A,B,C,D,E,F,G,H :in STD_LOGIC; MUX_OUT: out STD_LOGIC};end Mux8_1;architecture mux4_1_arch of Mux8_1 is beginprocess (SEL,A,B,C,D,E,F,G,H)begin case SEL is when "000"=>MUX_OUT<=A;when "001"=>MUX_OUT<=B;when "010"=>MUX_OUT<=C;when "011"=>MUX_OUT<=D;when "100"=>MUX_OUT<=E;when "101"=>MUX_OUT<=F;when "110"=>MUX_OUT<=G;when "111"=>MUX_OUT<=H;when others =>null;end case;end process;end mux4_1_arch;Write verilog code for 8 to 1 multiplexermodule mux(en, a, y,sel);input en;input[7:0]a;input[2:0]sel;output y;reg y;always@(en or a)beginif(!en)y=1'b0;else case(sel)3'b000:y=a[7];3'b001:y=a[6];3'b010:y=a[5];3'b011:y=a[4];3'b100:y=a[3];3'b101:y=a[2];3'b110:y=a[1];3'b111:y=a[0];endcaseendendmoduleOUTPUT 2.d(i)Program 2.d(i)Write VHDL code for 4 bit binary to gray converterlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity binary_Gray isport( a:in std_logic_vector(3 downto 0);b:out std_logic_vector(3 downto 0));end binary_gray;architecture behavioral of binary_gray is beginb(3)<=a(3);b(2)<=a(3)xor a(2);b(1)<=a(2)xor a(1);b(0)<=a(1)xor a(0);end behavioral;Write verilog code for 4 bit binary to gray convertermodule bintogrey(a,b)Input [3:0]a;Output [3:0]b;Reg [3:0]b;always@(a,b)Beginb[3]=a[3];b[2]=a[3]^a[2];b[1]=a[2]^a[1];b[0]=a[1]^a[0];endendmoduleOUTPUT 2.d(ii)Program 2.d(ii) Write VHDL code for 4 bit gray to binary converterlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity gray_bin isport( b:out std_logic_vector(3 downto 0);g:in std_logic_vector(3 downto 0));end gray_bin;architecture behavioral of gray_bin is beginb(3)<=g(3);b(2)<=g(3)xor g(2);b(1)<=g(3) xor g(2)xor g(1);b(0)<=g(3) xor g(2) xor g(1)xor g(0);end behavioral;Write verilog code for 4 bit gray to binary convertermodule graytbin(g,b);input [3:0]g;output [3:0]b;reg [3:0]b;always@(g)beginb[3]=g[3];b[2]=g[3]^g[2];b[1]=g[3]^g[2]^g[1];b[0]=g[3]^g[2]^g[1]^g[0];endendmoduleOUTPUT 2.eProgram 2.e Write VHDL code for 4 to 1 multiplexerlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux isPort(din: in std_logic_vector(3 downto 0);sel: in std_logic_vector(1 downto 0);dout:out std_logic);end mux;architecture Behavioral of mux isbeginprocess(din,sel)begincase sel iswhen "00"=>dout<=din(0);when "01"=>dout<=din(1);when "10"=>dout<=din(2);when "11"=>dout<=din(3);when others=>null;end case;end process;end Behavioral;Write verilog code for 4 to 1 multiplexermodule mux(din,sel,dout);input[3:0]din;input[1:0]sel;output dout;reg dout;always @(din,sel)begincase(sel)2'b00:dout=din[0];2'b01:dout=din[1];2'b10:dout=din[2];default:dout=din[3];endcaseendendmoduleOUTPUT 2.e(ii)Program 2.e(ii)Write VHDL module for n-bit comparatorlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity comparator isGeneric(N:integer:=3);Port(A,B:in STD_LOGIC_VECTOR(N downto 0); ALB,AGB,AEB:out STD_LOGIC);end comparator;architecture Comparator_arc of comparator isbeginprocess(A,B)beginif (A<B) then ALB<='1';else ALB<='0';end if;if (A>B) then AGB<='1';else AGB<='0';end if;if (A=B) then AEB<='1';else AEB<='0';end if;end process;end Comparator_arc;Write verilog module for n- bit comparatormodule comparator(A,B,alb,agb,aeb);input [3:0]A,B;output alb,agb,aeb;reg alb,agb,aeb;always@(A,B)beginif(A > B)agb=1;elseagb=0; if(A==B)aeb=1;elseaeb=0;if (A<B)alb=1;elsealb=0;endendmoduleOUTPUT 3Program 3Write VHDL module for n bit ALUlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity alu1 is Port(a,b :in std_logic_vector(2 downto 0); e: in std_logic; opcode : in std_logic_vector(2 downto 0); y :out std_logic_vector(2 downto 0));end alu1;architecture Behavioral of alu1 isbegin process(e,opcode) begin if(e='1')then case opcode is when "000"=>y<=a+b; when "001"=>y<=a-b; when "010"=>y<=not a; when "011"=>y<=a and b; when "100"=>y<=a nand b; when "101"=>y<=a or b; when "110"=>y<=a nor b; when "111"=>y<=a xnor b; when others=>null; end case; else y<=(others=>'0'); end if; end process; end Behavioral;Write verilog module for n bit ALUmodule aluvlg(e,a,b,opcode,y); input e; input [2:0] a,b; input [2:0] opcode; output [2:0]y; reg[2:0]y; always@(a or b or opcode) begin if (e==1) case(opcode) 3'd0:y=a+b; 3'd1:y=a-b; 3'd2:y= ~b; 3'd3:y=a&b; 3'd4:y=a|b; 3'd5:y= ~(a&b); 3'd6:y= ~(a|b); 3'd7:y= a^b; endcase else y=3'b000; end endmoduleOUTPUT 4(i)Program 4(i)Write VHDL module for full adder using dataflow styleslibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fulladdr isPort (a,b,c : in std_logic;sum,carry:out std_logic);end fulladdr;architecture Behavioral of fulladdr isbegin sum<=a xor b xor c; carry<=(a and b)or(b and c)or( c and a);end behavioral;Write verilog module for full adder using behavioral style module fulldavl(a,b,c,sum,carry); input a,b,c; output sum,carry; assign sum=a^b^c; assign carry=(a&b)(b&c)(c&a); endmoduleOUTPUT 4(ii)Program 4(ii)Write VHDL module for full adder using behavioral stylelibrary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity adder is Port (a,b,c :in std_logic; sum,carry:out std_logic); end adder; architecture Behavioral of adder is begin process(a,b,c) begin sum<=a xor b xor c; carry<=(a and b)or(b and c)or(c and a); end process;end Behavioral;Write verilog module for full adder using behavioral stylemodule fullbevl(a,b,c,sum,carry); input a,b,c; output sum,carry; reg sum,carry; always @(a,b,c) begin sum=a^b^c; carry=(a&b)(b&c)(c&a); end endmoduleOUTPUT 4(iii)Program 4(iii)Write VHDL module for full adder using structural styleSTRUCTURAL MODELNOTE: STEP1: File->new project->VHDL module:-type or2 program and save. STEP2: Under same project,go to create new source ->VHDL module->type half adder program and save. STEP3: Under same project, go to create new source ->VHDL module->type full adder program and save.STEP4:Create test bench wave and UCF for full adderlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity stfa is Port (x,y,cin :in std_logic; s,c :out std_logic);end stfa;architecture Behavioral of stfa iscomponent haport(a,b:in std_logic;s,c:out std_logic);end component;component or1port(a,b:in std_logic;c: out std_logic);end componentsignal c0,c1,s0 : std_logic;beginha0: ha portmap (y,cin,s0,c0);ha1: ha portmap (x,s0,s,c1);x3: or1 portmap (c0,c1,c);end behavioral; subprogram1library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity ha is Port (a,b :in std_logic; s,c :out std_logic);end ha;architecture Behavioral of ha isbegins<= a xor b;c<=a and b;end behavioral;subprogram 2library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity or1 is Port (a,b :in std_logic; c :out std_logic);end or1;architecture Behavioral of or1 isbeginc<= a or b;end behavioral;Write Verilog module for full adder using structural stylemodule full( a, b, c, sum, carry);input a , b, c;output sum , carry;wire c0,c1, s0;HA x0( b, c , s0, c0);HA x1( a, s0, sum, c1);or x2( carry, c0,c1);endmodulesubprogrammodule HA( x, y, sum1, carry1);input x, y;output sum1, carry1;assign sum1=x^y;assign carry1=x & y;endmoduleOUTPUT 5(i)Program 5(i)Write VHDL code for SR flip floplibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity SRFF isport(s:in std_logic; r:in std_logic; clk:in std_logic; q:buffer std_logic);end SRFF;architecture s_r_ff_arch of SRFF isbeginprocess(clk)beginif (clk='1'and clk'event) thenif(s='0' and r='1') then q<='0';elsif(s='0' and r='1')then q<='0';elsif(s='1' and r='0')then q<='1';elsif(s='1' and r='1')then q<='Z';end if;end if;end process;end s_r_ff_arch;Write a verilog code for SR flip-flopmodule sr1(sr,q,qnot,clk);input [1:0] sr;input clk;output q,qnot;reg q,qnot;initial beginq=0;qnot=1;endalways@(posedge clk)begincase (sr)2'b00: q=q;2'b01: q=0;2'b10: q=1;2'b11: q=1'bz;endcaseqnot=~q;endendmoduleOUTPUT 5(ii)Program 5(ii)Write VHDL code for D flip floplibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity DFF isport( clk:in STD_LOGIC; d: in STD_LOGIC ; q: out STD_LOGIC:='1');end DFF;architecture d_ff_arch of DFF isbeginprocess(clk)beginif(clk'event and clk='1')thenq<=d;end if;end process;end d_ff_arch;Write a verilog code for D flip-flopmodule sync_dff(d,clk,reset,q);input d,clk,reset;output q;reg q;initialq=1'b1;always@(posedge clk)if(~reset)q=1'b0;else q=d;endmoduleOUTPUT 5(iii) Program 5(iii)Write a VHDL code for JK flip-floplibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity JKFF is port(clk, j, k :in std_logic; q : buffer std_logic);end JKFF;architecture behavioral of JKFF isbeginprocess(clk,j,k)beginif(clk'event and clk='1')thenif(j='0' and k='0') thenq<=q;elsif(j='0' and k='1')thenq<='0';elsif(j='1' and k='0')thenq<='1';elsif(j='1' and k='1') thenq<=not q;end if;end if;end process;end behavioral;Write a verilog code for JK flip-flopmodule jkff(clk,reset,jk,q);input clk,reset; input [1:0]jk;output q; reg q; initial q=1'b0;always@(posedge clk) begin if(reset) q=0; else case(jk) 2'b00:q=q; 2'b01:q=0; 2'b10:q=1; 2'b11:q=~q; endcase endendmoduleOUTPUT 5(iv)Program 5 (iv) Write a VHDL module for T flip-floplibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity lit isport(clk,t :in std_logic; q : buffer std_logic);end lit;architecture Behavioral of lit isbeginprocess( t,clk)beginif(rising_edge (clk)) thenq<= t xor q;end if;end process;end Behavioral;Write a verilog code for T flip-flopmodule tffv(t,q,clk);input t,clk;output q;reg q;initialq=1;always@(posedge clk)begincase (t)1'b0: q=q;1'b1: q=~q;endcaseendendmoduleOUTPUT 6(i)Program 6 (i) Write a VHDL module for 4-bit binary counter with synchronous resetlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity sync isport(clk,reset: in std_logic; count:out std_logic_vector( 3 downto 0):="0000");end sync;architecture behavioral of sync isbeginprocess(clk, reset)variable temp:std_logic_vector(3 downto 0):="1010";beginif(clk'event and clk='1') thenif (reset='1')thentemp:="0000";elsetemp:=temp+1;end if;count<=temp;end if;end process;end behavioral;Write a verilog code for 4-bit binary counter with synchronous resetmodule syncrst(clk, reset, count); input clk; input reset; output [3:0] count; reg [3:0]count; initial count=4'b1010; always@(posedge clk) begin if (reset==1) count=4'b0000; else count=count+1; endendmoduleOUTPUT 6(ii)Program 6(ii) Write a vhdl code for 4 bit binary counter with asynchronous resetlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity sync isport(clk,reset: in std_logic; count:out std_logic_vector( 3 downto 0));end sync;architecture behavioral of sync isbeginprocess(clk, reset)variable temp: std_logic_vector(3 downto 0):="0000";beginif (reset='1')thentemp:="0000";elsif(clk='1')thentemp:=temp+1;end if;count<=temp;end process;end behavioral;Write a verilog code for 4-bit binary counter with asynchronous resetmodule asyncveri(clk, reset, count); input clk; input reset; output [3:0] count; reg [3:0] count; initial count=4'b0000; always @ (posedge clk) begin if (reset==1) count=4'b0000; else count=count+1; end endmoduleOUTPUT 6(iii)Program 6(iii) Write a VHDL code for BCD counterlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity bcdcnt isport(clk,reset: in std_logic; count:inout std_logic_vector( 3 downto 0):="1001");end bcdcnt;architecture behavioral of bcdcnt isbeginprocess(clk, reset)beginif(clk='1' and clk'event)thenif (reset='1')thencount<="0000";elsif(count="1001")thencount<="0000";elsecount<=count+1;end if;end if;end process;end behavioral;Write a verilog code for BCD countermodule bcdverilog(clk, reset, count); input clk; input reset; output [3:0] count; reg [3:0] count; initial begin count=4'b1001; end always @(posedge clk) begin if(reset==1) count=4'b0000; else if (count==4'b1001) count=4'b0000; else count=count+1; end endmodule PART BProgram 1 Write a HDL code for displaying messages on seven segment displaylibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity key isport (scan_l : out std_logic_vector (3 downto 0);read_l_in : in std_logic_vector (3 downto 0); clk : in std_logic;disp_cnt : out std_logic_vector (3 downto 0);disp: out std_logic_vector (6 downto 0));end key;architecture behavioral of key issignal disp1:std_logic_vector ( 6 downto 0);signal scan_l_sig : std_logic_vector (3 downto 0);signal clk_div :std_logic_vector (11 downto 0);signal clk_4k : std_logic;signal cnt_2bit :std_logic_vector( 1 downto 0);signal read_l : std_logic_vector (3 downto 0);beginprocess (clk)beginif clk='1' and clk'event thenclk_div <= clk_div + '1';end if;end process;clk_4k<=clk_div(11);process (clk_4k)beginif clk_4k='1' and clk_4k'event thencnt_2bit <=cnt_2bit + '1';end if;end process;process (cnt_2bit)begincase cnt_2bit iswhen "00" => scan_l_sig <="0001";when "01" => scan_l_sig <="0010";when "10" => scan_l_sig <="0100";when "11" => scan_l_sig <="1000";when others => null;end case;end process;read_l <=read_l_in;scan_l <= scan_l_sig;disp_cnt <="1110";process (scan_l_sig, read_l)begincase scan_l_sig iswhen "0001" => case read_l iswhen "0001" => disp1<="1111110";when "0010" => disp1<="0110011";when "0100" => disp1<="1111111";when "1000" => disp1<="1001110";when others=> disp1<="0000000";end case;when "0010" => case read_l iswhen "0001" => disp1<="0110000";when "0010" => disp1<="1011011";when "0100" => disp1<="1111011";when "1000" => disp1<="0111101";when others=> disp1<="0000000";end case;when "0100" => case read_l iswhen "0001" => disp1<="1101101";when "0010" => disp1<="1011111";when "0100" => disp1<="1110111";when "1000" => disp1<="1001111";when others=> disp1<="0000000";end case;when "1000" => case read_l iswhen "0001" => disp1<="1111001";when "0010" => disp1<="1110000";when "0100" => disp1<="0011111";when "1000" => disp1<="1000111";when others=> disp1<="0000000";end case;when others =>null;end case;end process;disp<=disp1;end behavioral;UCF file ( user constraints)NET “clk” LOC=”p52”;NET “disp_cnt<0>” LOC=”p23”;NET “disp_cnt<1>” LOC=”p24”;NET “disp_cnt<2>” LOC=”p26”;NET “disp_cnt<3>” LOC=”p27”;NET “disp <0>” LOC=”p18”;NET “disp <1>” LOC=”p17”;NET “disp <2>” LOC=”p15”;NET “disp <3>” LOC=”p14”;NET “disp <4>” LOC=”p13”;NET “disp <5>” LOC=”p12”;NET “disp <6>” LOC=”p1”;NET “read_l_in <0>” LOC=”p112”;NET “read_l_in <1>” LOC=”p116”;NET “read_l_in <2>” LOC=”p119”;NET “read_l_in <3>” LOC=”p118”;NET “scan_l <0>” LOC=”p123”;NET “scan_l <1>” LOC=”p131”;NET “scan_l <2>” LOC=”p130”;NET “scan_l <3>” LOC=”p137”;Program 2 Write a HDL code to control speed, direction of DC motorlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;library UNISIM;use UNISIM.vcomponents.All;entity dcmtr isgeneric (bits : integer :=8);port (clk : in std_logic;reset,dir : in std_logic;pwm : out std_logic_vector(1 downto 0);rly : out std_logic ; row : in std_logic_vector(0 to 3));end dcmtr;architecture behavrioral of dcmtr issignal counter : std_logic_vector(bits-1 downto 0):="11111110";signal div_reg : std_logic_vector(16 downto 0);signal dclk,ddclk,datain,tick : std_logic;signal duty_cycle : integer range 0 to 255; signal row1: std_logic_vector(0 to 3);beginclk_div : process (clk, div_reg)beginif(clk'event and clk='1') thendiv_reg <= div_reg+1;end if;end process;ddclk <= div_reg(12);tick <= row(0) and row(1) and row(2)and row(3);process(tick)begin if falling_edge (tick) thencase row iswhen "1110" => duty_cycle <=255;when "1101" => duty_cycle <=200;when "1011" => duty_cycle <=150;when "0111" => duty_cycle <=100;when others =>duty_cycle <= 100;end case;end if ;end process;process(ddclk,reset)beginif reset ='0' thencounter <= (others=>'0');pwm <="01";elsif ( ddclk'event and ddclk='1')thencounter <=counter+1;if counter >= duty_cycle thenpwm(1)<='0';elsepwm(1)<='1';end if ;end if;end process;rly <= dir;end behavrioral;UCF file ( user constraints)NET “clk” LOC=”p52”;NET “dir” LOC=”p76”;NET “pwm<0>” LOC=”p4”;NET “pwm<1>” LOC=”p141”;NET “reset” LOC=”p74”;NET “rly” LOC=”p44”;NET “row<0>” LOC=”p69”;NET “row<1>” LOC=”p63”;NET “row<2>” LOC=”p59”;NET “row<3>” LOC=”p57”;Program3 Write a HDL code to control speed,direction of stepper motorlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity stprmtr isport(clk,reset:in std_logic; dout : out std_logic_vector(3 downto 0); row : in std_logic_vector(1 downto 0);dir : in std_logic);end stprmtr;architecture behavioral of stprmtr issignal clk_div :std_logic_vector (25 downto 0);signal clk_int : std_logic;signal shift_reg : std_logic_vector (3 downto 0);beginprocess(clk)beginif rising_edge (clk) then clk_div <=clk_div + '1';end if ;end process;clk_int<=clk_div(21) when row="00" elseclk_div(19) when row="01" elseclk_div(17) when row="10" elseclk_div(15) ;process(reset,clk_int,dir)begin if reset ='0' thenshift_reg<="1001";elsif rising_edge(clk_int)thenif dir='0' thenshift_reg<=shift_reg(0)& shift_reg(3 downto 1);elseshift_reg<=shift_reg(2 downto 0)& shift_reg (3);end if;end if;end process;dout<=shift_reg;end behavioral;UCF file( user constraints)NET “clk” LOC=”p52”;NET “dir” LOC=”p76”;NET “dout<0>” LOC=”p141”;NET “dout<1>” LOC=”p2”;NET “dout<2>” LOC=”p4”;NET “dout<3>” LOC=”p5”;NET “reset” LOC=”p74”;NET “row<0>” LOC=”p77”;NET “row<1>” LOC=”p79”;Program 4 Write a HDL code to generate different waveforms(i)Square wavelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity sqwave isport (clk : in std_logic; reset : in std_logic;dac_out : out std_logic_vector (0 to 7));end sqwave;architecture behavioral of sqwave issignal temp : std_logic_vector( 3 downto 0);signal counter : std_logic_vector(0 to 7); signal en :std_logic;beginprocess(clk)beginif rising_edge (clk) thentemp <=temp+'1';end if;end process;process(temp(3),reset)beginif reset='1' thencounter <= "00000000";elsif rising_edge (temp(3)) thenif counter<255 and en='0' thencounter <=counter + 1;en <='0';dac_out<="00000000";elsif counter =0 thenen <='0';elseen <='1';counter <=counter -1;dac_out <="11111111";end if;end if;end process;end behavioral;(ii)Triangular wavelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity triwave isport ( clk : in std_logic ; reset : in std_logic;dac_out : out std_logic_vector (0 to 7));end triwave;architecture behavioral of triwave issignal counter : std_logic_vector (0 to 8);signal temp : std_logic_vector (3 downto 0);signal en : std_logic;beginprocess (clk)beginif rising_edge (clk) thentemp <=temp + '1';end if;end process;process(temp(3))beginif reset ='1' thencounter <="000000000";elsif rising_edge (temp(3)) thencounter <=counter + 1;if counter(0)='1' thendac_out <=counter (1 to 8);elsedac_out <=not(counter (1 to 8));end if;end if;end process;end behavioral;(iii) RAMP WAVElibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity ramp isport ( clk : in std_logic; reset : in std_logic;dac_out : out std_logic_vector ( 0 to 7));end ramp;architecture behavioral of ramp issignal temp : std_logic_vector (3 downto 0);signal counter : std_logic_vector ( 0 to 7);signal en : std_logic;beginprocess (clk)beginif rising_edge (clk) thentemp <=temp + '1';end if;end process;process (temp(3))beginif reset = '1' thencounter <="00000000";elsif rising_edge (temp (3)) thencounter <=counter + '1';end if;end process;dac_out <= counter;end behavioral;(iv) SAWTOOTH WAVElibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity sawtooth isport (clk : in std_logic ; reset : in std_logic;dac_out : out std_logic_vector (0 to 7));end sawtooth;architecture behavioral of sawtooth issignal temp: std_logic_vector( 3 downto 0);signal counter : std_logic_vector( 0 to 7);signal en :std_logic;beginprocess(clk)beginif rising_edge (clk) thentemp <=temp +'1';end if;end process;process (temp(3))begin if (reset ='1') thencounter <= "00000000";elsif rising_edge(temp(3)) thencounter <=counter +8;end if ; end process;dac_out <= counter; end behavioral;UCF file( user constraints)NET “clk” LOC=”p52”;NET “dac_out<0>” LOC=”p21”;NET “dac_out<1>” LOC=”p18”;NET “dac_out<2>” LOC=”p17”;NET “dac_out<3>” LOC=”p15”;NET “dac_out<4>” LOC=”p14”;NET “dac_out<5>” LOC=”p13”;NET “dac_out<6>” LOC=”p12”;NET “dac_out<7>” LOC=”p1”;NET “rst” LOC=”p74”; ................
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