ANNA UNIVERSITY :: CHENNAI 600 025

Design of traffic light controller using verilog and above tools . Design and simulation of pipelined serial and parallel adder to add/ subract 8 number of size, 12 bits each in 2's complement . Design and simulation of back annotated verilog files for multiplying two signed, 8 bit numbers in 2's complement. ................
................

In order to avoid copyright disputes, this page is only a partial summary.