QUESTION & ANSWER

QUESTION & ANSWER

(This file will be regularly updated until one day before the Final Examination – please take note) ---Current Update 06/11/07

1. Registers x and y are declared as reg [2:0] x,y;. x and y have initial values of 1 and 2 respectively. Find the value of x and y after each of the following Verilog codes have been executed.

(a) y = x && y;

x = y & x;

Ans: x = 1, y = 1

(b) x ................
................

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