Digital System Design



Digital System Design

Course Outline

|Week |Course |Speaker |Note |

|1st (2/20) |Overview DSD Course |Prof. Wu |Introduction |

|2nd (2/27) |Overview of Verilog HDL | |Hw1 |

|3rd (3/5) |Modeling and Verification | |Hw2 |

|4th (3/12) |Basic building blocks of a MIPS CPU(I) | |Lab1 |

|5th (3/19) |Behavior Models | |Hw3 |

|6th (3/26) |Synthesis of Combinational Circuits | |Hw4 |

|7th (4/2) |彈性放假 | |(6/14補課) |

|8th (4/9) |Basic building blocks of a MIPS CPU(II) | |Lab2,(Lab1 deadline) |

|9th (4/16) |期中考 | |期中考週 |

|10th (4/23) |Synthesis of Sequential Circuits | |Hw5 |

|11th (4/30) |State machines & Datapath Controllers | |Hw6 |

|12th (5/7) |ALU design/Write final project proposal | |Lab3,(Lab2 deadline) |

|13th (5/14) |From single module to complex design | |Hw7/Submit proposal |

|14th (5/21) |Algorithm and Architecture Design | |Hw8 |

|15th (5/28) |Improving Timing, Area, and Power | |(Lab3 deadline) |

|16th (6/4) |Coding Style | | |

|17th (6/11) |Industry Design Guidelines | | |

|18th (6/14) |Final project report 1 | | |

|18th (6/18) |Final project report 2 | |期末考週 |

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