Extending SystemVerilog Data Types to Nets
Verilog-2001 provides arbitrary fixed length arithmetic using reg data types. The reg type can have bits at X or Z, however, and so are less efficient than an array of bits, because the operator evaluation must check for X and Z, and twice as much data must be stored. SystemVerilog adds a bit type which can only have bits with 0 or 1 values. ................
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