EE 3120: Digital Circuits Lab



EE 3120: Digital Circuits Lab

LAB 1: COMBINATIONAL LOGIC DESIGN USING FPGAs

Objectives

The objectives of this laboratory assignment are:

• To get familiar with the Xilinx Foundation Series Tools for the design of logic circuits described using an HDL.

• To understand and use Verilog HDL for the design of simple combinational logic circuits.

• To learn how to implement combinational logic circuits using FPGA prototyping boards.

Laboratory Instructions

• Create the Verilog source file(s) for your designs before coming to the lab. You can use the Xilinx HDL editor or any text editor to create your files. Remember to bring these files to the lab on a floppy disk, or to save these files on your home area.

• Create a directory with your name on your lab PC. Use this directory to create your project, store your results, bitstreams, etc. during the lab session.

• Use the Xilinx software to create a new project in your directory on the C drive and then copy your Verilog (.v) to that new project directory.

• Remember to add your Verilog file to this new project (see the EE3120 Laboratory Tutorial on



for details).

• Perform functional simulation of your design and have it checked by the lab instructor or your TA before proceeding with the implementation. In case you modify your original Verilog source file, remember to copy it back to your floppy disk, or save it on your home area.

• If the circuit works as expected, implement it using the prototyping board assigned to you.

• Use switches and LEDs to test and demonstrate your circuit to the lab instructor or your TA.

• Before you leave the lab please remove any files or directories you created on your lab PC (only if you used the local drive C) and leave your workplace at least as clean and tidy as you found it.

Pre-lab Work (due at the start of this lab)

• Complete your design and its Verilog implementation and bring your Verilog program on a floppy disk. You can use any text editor to create a Verilog file. If you have any problems with Verilog syntax and other pre-lab related issues, please resolve them with the instructor or your TA before coming to the lab. Your TA may not be able to help you with these issues during the lab session.

• Simulate your designs and make sure they are working as per the given specifications.

• At the start of this lab submit a hardcopy of all your Verilog programs and design diagram (if any) to your TA or the lab instructor. This pre-lab work you submit will be graded as a part of this laboratory assignment. Incorrect or incomplete designs and Verilog programs will not receive full credit for pre-lab work.

Laboratory Report Instructions (due at the start of lab2)

• Your report should be typed and prepared as per the guidelines given on the EE 3120 web page



• For each design of this lab, submit the following:

• Details of any manual Boolean equation minimization or manipulation that was done by you.

• Documented listing of your Verilog source file(s) with appropriate pin assignments in the same or separate file(s).

• Simulation waveforms: Label the waveforms to indicate proper operation of your circuit(s).

Design Problems

Using the Xilinx CAD tools, design, test and demonstrate combinational logic circuit(s) which implement the following logic functions. You may implement all the functions using one or multiple Verilog files. Your circuits should be as small as possible.

Notation:

+,| logic or a bar on top of a variable notates logic inversion (not)

& logic and / logic inversion (not)

^ logic xor

= equal

/= not equal

1. Manually minimize and implement the following functions:

• [pic]

• G(x,y,z) = x^y | y^z | x^ z

2. Use the Verilog compiler and the available logic synthesizer to minimize and implement the following functions:

• H(v,w,x,y,z) = (/v | w) & x if y^z=0

(v ^ w) | /x if y /= z

• G

|x |y |z |G |

|0 |0 |0 |0 |

|0 |0 |1 |1 |

|0 |1 |0 |1 |

|0 |1 |1 |1 |

|1 |0 |0 |0 |

|1 |0 |1 |0 |

|1 |1 |0 |0 |

|1 |1 |1 |1 |

3. Design the controller for a lawn sprinkler system. The controller accepts three inputs: START, DRYNESS, and RAIN. It produces two outputs: ON, and FLOW. The description of input/output signals is as follows:

• START = 1. Start sprinkler in the morning (ON=1), if and only if it is needed.

• DRYNESS : is a 2-bit input: 00 = too dry, 01 = dry, 10 = wet, and 11 = fully watered.

• RAIN = 1. It is raining and the sprinkler should not be turned on.

• ON = 1. Turn on the sprinkler system.

• FLOW is a 2-bit output which controls the flow of water: 11 = maximum flow, 10 = medium flow, 01 = drip, and 00 = no flow.

The sprinkler system is turned on (set ON=1), if START =1. The lawn is not fully watered and it is not raining. The output flow should be “maximum” when the lawn is too dry, “medium when it is dry, and “drip” when it is wet. The sprinkler should be turned off when the lawn is fully watered. Design this controller using Verilog and implement it on the prototyping board.

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