Modeling a Processor



CPE 626, Spring 2002: Modeling a Processor using Verilog

SISC – Small Instruction Set Computer

SISC Instruction Set

The SISC instruction set consists of 10 defined instructions:

|NOP |No Operation |

|BRA |Branch Absolute (conditional/unconditional) |

|LOAD |Load Register |

| |(from indirect register or immediate to direct register) |

|STORE |Store Register |

| |(to indirect register from direct register or immediate) |

|ADD |Addition (Rdst = Rdst + Rsrc) |

|MUL |Multiplication (Rdst = Rdst * Rsrc) |

|NOT |Bitwise Invert (Rdst = ~ Rsrc) |

|SHF |Logical Shift (Rdst = Rdst >> Rn) |

|ROT |Logical Rotate (Rdst = Rdst >> Rn) |

|HLT |Halt Processor |

Block Diagram of Internal Structure

[pic]

Machine Characteristics

|Word length |32 bit |

|General purpose registers |16 * 32 bit |

|Address space |2^12 = 4096 words = 16 KB |

|Addressing resolution |word |

| Instruction set |LOAD/STORE-architecture |

|Immediate operand lengths |12 bit |

|Addressing modes |immediate |

| |register-direct |

| |register-indirect |

SISC Encoding

[pic]

| |31:28 |27:24 |23:12 |11:0 |

|NOP |0 |x |xxx |xxx |

|BRA |1 |cc* |xxx |#addr |

|LOAD ind |2 |0 |(Rsrc) |Rdst |

|LOAD imm |2 |8 |#val |Rdst |

|STORE reg |3 |0 |Rsrc |(Rdst) |

|STORE imm |3 |8 |#val |(Rdst) |

|ADD |4 |0 |Rsrc |Rdst |

| |4 |8 |#val |Rdst |

|MUL |5 |0 |Rsrc |Rdst |

| |5 |8 |#val |Rdst |

|NOT |6 |0 |Rsrc |Rdst |

| |6 |8 |#val |Rdst |

|SHF |7 |0 |Rn |Rdst |

| |7 |8 |#n |Rdst |

|ROT |8 |0 |Rn |Rdst |

| |8 |8 |#n |Rdst |

|HLT |E |x |xxx |xxx |

*cc can be one of the following values:

|CC | |

|0 |unconditional branch |

|1 |branch on carry bit set |

|2 |branch on even value |

|3 |branch on odd parity |

|4 |branch on zero bit set |

|5 |branch on negative bit set |

Status Register:

|4 |3 |2 |1 |0 |

|Neg |Zero |Par |Even |Carry |

SISC Behavioral Model

/***************************************************************

SISC processor without pipelining

from Sternheim et al,

"Digital Design and Synthesis with Verilog HDL"

***************************************************************/

module system ;

// Declare parameters

parameter CYCLE = 10 ; // Cycle Time

parameter WIDTH = 32 ; // Width of datapaths

parameter ADDRSIZE = 12 ; // Size of address fields

parameter MEMSIZE = (1> i) : (src2 0) begin

if (dir == `RIGHT) begin

result = src2 >> 1 ;

result[WIDTH-1] = src2[0] ;

end

else begin

result = src2 = `ADD) && (`OPCODE < `HLT)) begin

if (`DSTTYPE == `REGTYPE) RFILE[`RDST] = result ;

else MEM[`DST] = result ;

end

end

endtask

// Debugging aid ....

task apply_reset ;

begin

reset = 1 ;

#CYCLE

reset = 0 ;

pc = 0 ;

end

endtask

task disprm ;

input rm ;

input [ADDRSIZE-1:0] adr1, adr2 ;

begin

if (rm == `REGTYPE) begin

while (adr2 >= adr1) begin

$display("REGFILE[%d]=%d\n",adr1,RFILE[adr1]) ;

adr1 = adr1 + 1 ;

end

end

else begin

while (adr2 >= adr1) begin

$display("MEM[%d]=%d\n",adr1,MEM[adr1]) ;

adr1 = adr1 + 1 ;

end

end

end

endtask

/******************************************************************/

// Initial and always blocks

// NOTE: The $readmemb statement should be edited to include

// the full path and name of the SISC program file!

/******************************************************************/

initial begin : prog_load

$readmemb("sisc_prog.count",MEM) ;

$display("\t\tTIME\tPC RFILE[0] RFILE[1] RFILE[2]") ;

$monitor("%d %d %h %h %h",$time,pc,RFILE[0],RFILE[1],RFILE[2]) ;

apply_reset ;

end

always begin : main_loop

if (!reset) begin

#CYCLE fetch ;

#CYCLE execute ;

#CYCLE write_result ;

end

else #CYCLE ;

end

endmodule

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