Problem Set 1

Design a Verilog task that uses your function from part a to implement a vector adder as described previously. Note: The entire vector addition takes a single cycle to perform. Verify the whole design by applying the following operand combinations. Operand A Operand B 32’h00_00_00_00 32’hFF_FF_FF_FF 32’h0F_0F_0F_0F 32’hF1_F1_F1_F1 ................
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