Sri Krishna College of Technology

Verilog Synthesis: Synthesis of combinational logic and sequential logic - synthesis of explicit and implicit state machines- Synthesis of gated clocks and clock enables -synthesis of Loops Total Hours: 45 Text Books: 1 D. Ciletti, “Advanced Digital Design with the VERILOG HDL” PHI.2008 2 J. Bhaskar, “A VHDL Synthesis Primer”, BS ... ................
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