Mentor Graphics Tutorial: from VHDL to Silicon layout ...



Mentor Graphics Tutorial: from VHDL to Silicon layout

Aleksandar Milenkovic

Electrical and Computer Engineering

The University of Alabama in Huntsville

Sparkman dr. 301, AL 35899

Email: milenka@ece.uah.edu

URL:

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Introduction

This tutorial describes a complete ASIC design flow from VHDL to silicon layout using software from Mentor Graphics Corp. In this tutorial we will design an 8-bit adder described in Figure 1. We assume that the model has already been verified using ModelSim (see ).

|library IEEE; |

|use IEEE.std_logic_1164.all; |

|use IEEE.std_logic_unsigned.all; |

|entity ADDER is |

|generic (N : in integer := 8); |

|port ( |

|A, B : in std_logic_vector(N-1 downto 0); |

|CI : in std_logic; |

|S : out std_logic_vector(N-1 downto 0); |

|COUT : out std_logic); |

|end ADDER; |

|architecture RTL of ADDER is |

|signal RESULT : std_logic_vector(A'length downto 0); |

|begin |

|RESULT All from the top menu bar to see the automatically generated floor plan. You will see a series of boxes enclosed by solid green bars along each edge. The boxes indicate the rows into which cells will be organized. The solid bars indicate edges of the cells along which physical ports will be placed.

Step 4. Placing the standard cells

In the Place & Route palette go to Autoplc section and choose StdCel. Accept the default options in the dialog box. You should see individual cells placed in the floorplan boxes. Cell locations are determined by their interconnectivity. Cells which share connections are placed near one another. You may wish to experiment with the results obtained thus far by selecting different Autofloorplan and Autoplace options.

Step 5. Placing ports

From the Autoplc section of the Place & Route palette select Ports. You can allow the options to default for now, but you may wish to experiment with them later. You will see lightly shaded areas along the port bars at the edge of the layout.

At this point, it is assumed that you have arrived at a satisfactory initial placement for all cells of the layout. Prior to autorouting the interconnect, you may wish to observe a "rats nest" view of the signals connecting the various cells. This is sometimes useful to engineers for determining sources of routing congestion. To observe a rats nest of signal connections, select Connectivity -> Net -> Restructure -> All signal. It may look a little messy, but keep in mind that it doesn't change the layout whatsoever.

Step 6. Route the IC cell

From the Place & Route palette select "All" from the "Autorou" subsection. A submenu will appear in the editing window. Select "Options" and "Expert" options and select "Channel Over Cell Routing". From the "OCR" options menu set the step size to 0.5 and the "Operation Mode Type" to "Center Weighted". Click OK on all the forms and begin autorouting. Depending on the size of the design this may take several minutes. When the process has completed the mouse pointer changes from an hourglass back to an arrow and the results of the process are in a text transcript found in the current directory.

Step 7. Find and route overflows

This step is necessary even if overflows don’t immediately appear in the routed layout. Several small overflows may still exist, which can be expected for larger designs. When zoomed out small overflows may not be viewable, but may still exist. To select all overflows in the design, enter command "check over". In the form window that appears select "All" and OK the form. Next, from the Place and Route palette menu select "Overflw". If the response "An object of type Overflow must be selected" appears in the status block, there are no overflows to route. Otherwise, the overflows should be routed, manually or automatically.

Save the cell layout: Save the layout by File -> Cell -> Save Cell -> Current Context. You may save the layout and exit the ICgraph session at any time. To re-load the layout later, choose open from the IC staton palette. If you wish to make changes to the cell after you save, you must select File -> Cell -> Reserve Cell -> Current Context.

Step 8. Compacting

The autorouter’s objective is to complete as many connections in the design as possible with less regard for wasted area. A layout compactor is available allowing you to “squashe” things together where there is a little bit of unused space. To run compactor, go to PR Edit section of the Place & Route palette and select Compct. We want to compact in both the horizontal and vertical dimensions, so do this twice: once selecting down direction, and then again selecting left direction. Do not do this more than once along a given axis – it rarely gives any improvement, and can lead to layout errors.

Step 9. Save the IC cell

Save the layout. This completes the automatic layout of the core logic which might be similar to the following one

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Figure 5. The automatically generated layout of the core logic.

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Verifying the IC layout using the schematics (LVS)

Although the automatic tools performed the layout in Correct by Construction mode, it is always safer to verify the layout for correctness in terms of both layout design rules and connectivity to insure consistency between the various tools used. This establishes a system of "checks and balances" that increases the overall confidence in the design.

First we check for layout design rule errors using ICrules, then we verify the layout by double-checking it against the transistor level representation of the logic schematics. This procedure is very similar to earlier tutorials.

Step 1: Check Layout Design Rules

From the main ICstation palette select ICrules, then select Check from the ICrules palette. A prompt box will appear at the lower left of the screen. Click on OK to proceed with the check. Optionally, if you are using the ADK Edit menu, you can use Drc->Check.

Step 2: Fix any Design Rule Errors

When the check is complete, design rule errors in the layout will be reported in the message bar at the bottom of the ICstation window. The first one can be shown by selecting "First" in the palette (or DRC->First in the ADK Edit palette). The rest can be viewed by clicking on "Next".

For example, for our design we will get the following message:

”DRC completed. Total RuleChecks: 80; Total Results 26; Total original geometries 5000; ....”.

This means that there are 26 DRC errors. By selecting “First” in the IC Rules palette you will get the following:

“[Current DRC] Result 1 of 26 in Rule check bad_port: Port must be completely covered with Metal.”.

The autorouter failed to cover completely the ports with the respective metal layers (a very thin strip is missing). If you inspect layout you will see that for all ports we have two polygons implemented Metal1 and Metal1.port layers or in Metal2 and Metal2.port layers. There is no overlapping between the two, so you should cover Metal1.port or Metal2.port polygons with Metal1 or Metal2 shapes. To do this, select Easy Edit palette and Add Objects subsection and fix all ports (26 in this case). Repeat the DRC check; you should get 0 DRC errors.

Step 3: Layout versus Schematic test (LVS)

Verify the layout for consistency with the transistor level schematic of the design. Go back to the main ICstation palette and selecting the ICtrace(M) (mask level LVS) option. Click on LVS in the ICtrace(M) palette. In the dialogue box, enter the LVS viewpoint ($MGC_WD/work/ADDER_8/lvs) for "Source Name" and then click on the Setup LVS button. In the Setup LVS form, change the following items and click OK:

Ground Names: VSS GND (note that VSS and GND must be in separate boxes)

Recognize Gates: Yes

(If you’re already in the ADK Edit menu, you can go directly to these dialogue boxes by clicking on LVS)

Step 4: View the connectivity check results

When the check is complete, the bottom message bar will read "Mask results database loaded". To view the results, you can select Report -> LVS from the palette menu. Look for that magic smiley face. If a nasty X appears instead, go back and make certain that the LVS viewpoint has been properly setup and follow the above procedures again. When doing so, look for potential sources of discrepancies between the schematic and how the layout was generated.

Since the example is so simple, take a look at the layout to see how autorouter has handled the routing, size of VDD and GND ports and tracks, and how the cells are connected.

Step 5: Save the IC layout

Save the IC layout.

Step 6: Relative location of the ports

From the point of view of the structure of the complete integrated circuit it is important to know the relative location of the ports. Select/unselect (F2 key) connection to every port and obtain the relative port positions which might be similar to the following.

| |S(0) B(0) CI A(0) A(1) S(4) S(5) A(4) B(4) | |

|S(1) | |B(5) |

|B(1) | |A(5) |

|A(2) | |Vdd |

|Gnd | |S(6) |

|B(2) | |A(6) |

| | |S(7) |

| |S(3) B(3) A(3) S(2) B(6) B(7) A(7) Cout | |

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Preparing for Fabrication - Adding Padframes in the schematics

The ports on your core logic are very small - typically a few square lambda in area. It is very difficult to bond a metal wire from an outside pin (a couple of mm's wide) to a port that is at the order of micrometres. Besides, the layout must also provide binding area for holding this wire onto the silicon cell. In order to prevent electrostatics damages, buffers and discharge diodes may be inserted into the ports to create tough I/O to interface.

This part is where you see metal pins (with decreasing width) drawing from outside I/O to the silicon layout in many layout photos.

Step 1: Generate symbol for your core logic

You need to generate a symbol for each piece of core logic (component) that you want to use. You will also need a completed IC layout for each component for which you have a symbol. These can be SDL or standard cell designs or a combination of both. Since we have already created the layout, we should create a symbol for the example by starting design architect in the design directory (as working directory), open the schematic, then Miscellaneous -> Generate Symbol. Make sure you click Yes on "Replace existing?". Leave all default options.

Check the symbol. Save the symbol. Close all symbol windows and schematic windows.

Step 2: Create new schematic

Now open a new schematic.

Change the component name to "final". Click on "Options" and click "New Sheet". OK all the forms and an empty schematic window will open. Use "Choose Symbol" on the palette to bring in the design part(s) and wire them together if necessary. In this example, choose adder (since we don't have any other logic to wire up). You need to add the phy_comp property (string) to the symbol. The value of phy_comp needs to be the name of the IC cell that you created. Select the symbol in your schematic and hit RMB (Right Mouse Button) and choose Properties -> Add. “New Property Name” is "phy_comp", Property Value is "adder", “Property Type” is "String". OK the form and choose any location to show this value.

Perform a check -> sheet and just ignore the unconnected pin warnings. Save the schematic.

In the ADK Library menu choose the pads to use from the appropriate library for your technology. Based on the technology, there may be different types of pads available. You can only use one set of technology pads and it must agree with the technology of your design. In this case, choose AMI 0.5.

Step 3: Add pads

Insert 17 "In" pads for the inputs ( A(7-0), B(7-0), Cin). Connect the DataIn pin of the pads to your input ports. Insert a "Out" pads for the outputs. Connect the DataOut pin of the pad to your output port. Insert 3 Vdd pads and 3 Gnd pads into the schematic for power and GND connections. Connect together all Vdd pads and all Gnd pads. No need to wire them up to your logic.

At this stage we have not yet allocated the ports of the core logic to the pins of the padframe. The properties “PINXX” of the I/O pads must be changed so that “XX” is replaced with the pin number of the padframe. The size of the padframe we will be using is the 40-pin tiny-chip padframe. See the mosis website for more details.

Step 4: Pin-port allocation

In order to allocate pins of the padframe to ports of the core logic we prepare the following diagram:

| |15 | |6 | |

|16 | |S(0) B(0) CI A(0) A(1) S(4) S(5) A(4) B(4) | |5 |

| |S(1) | |B(5) | |

| |B(1) | |A(5) |.. |

| |A(2) |Core |Vdd |1 |

| |Gnd | |S(6) |40 |

| |B(2) | |A(6) |.. |

| | | |S(7) | |

|25 | |S(3) B(3) A(3) S(2) B(6) B(7) A(7) Cout | |36 |

| |26 | |30 | |

Based on the above diagram the following pin-port allocation is used:

Change the property PINXX on the pads to replace XX with the pin number as in the table above (use shift-F7 key).

Check carefully, fix all the errors and save the schematic. The complete circuit should look like the one in Figure 6.

Step 4: Save and quit the Design Architect

Now quit the Design Architect.

Step 5: Create viewpoints

Make the design view points for the final schematic:

$ adk_dve final

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Figure 6. A schematic of the integrated circuit with I/0 pads.

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Preparing for Fabrication - Generating Padframe in the layout

You should be in the design directory, and set it as working directory if you have not done so already.

Step 1: Invoke the IC station

$ adk_ic

Step 2: Create a new layout cell

Create a new layout cell for the new schematics. The cell name should be the same as the new schematic (final in this case). Attach Library is $ADK/technology/ic/ami05. Process is $ADK/technology/ic/ami05. Rules File is $ADK/technology/ic/ami05.rules. Choose Connectivity? With connectivity. The EDDM Schematic Viewpoint MUST be the layout viewpoint under your design (ie. $MGC_WD/final/layout). Click "Logic Loading Options" and choose Flat on "Logic Loading". Accept the default options, and click OK to close all the forms.

Step 3: Select the core logic

Since we have saved the completed cells in the current working directory, you will need to set your search path from the IC Station Setup->SDL to the current working directory. The search path initially should look something like this: $ADK/technology/ic/ami05_via $PROJECT/cells. Change it to just "." for only the current, or working directory. If you have other cells to add in other directory, you will have to change this option all the time. It is better to gather (copy) all the cells into the working directory.

Go to the ADK Edit palette menu and click on Open to open the logic source window. You should see your schematic in a new window.

Select the core logic (if you have more than one piece, select them all). In this case, select sample.

Then click on Inst on the DLA Logic palette to place the cells into your layout window. Remember, you must have previously designed these cells and they must have the name of the phy_comp property on your symbol.

Step 4: Generate padframe

Once you have placed the core logic block(s), you are ready to generate the padframe. Do not place the pads, yourself. Use menu ADK -> Generate Padframe -> AMI 0.5 (or the appropriate technology for your design) pulldown menu to generate the padframe. Make life easy on yourself. NEVER EDIT OR RELOCATE PAD CELLS.

View the entire cell now, to see the padframe and your logic (Shift-F8). You should see the entire padframe with corner pads, the pads you asked for and spacer pads for all the empty spaces (or analog pads for the case of the ami12 technology). You will also see overflows connecting the ports to the corresponding padframe pins.

At this point you might notice that your core logic should be rotated, flipped or moved to make routing easier. Do that now, but be careful not to move the pads.

Step 5: Route the pads to the core

After finalizing the placement of the core logic, you can route the pads to the core. You can do this manually or automatically. To autoroute, click on P&R on the ADK Edit palette menu to bring up the Place & Route palette menu. Then click on All under Autorou. On the prompt-bar that appears click Options and unselect Expand Channels from the menu. Click OK on the menu and prompt-bar to autoroute the pads.

Now take a look at the final layout and fix any problems. For example, you might not like the width or placement of the power busses. You can edit these routes (or opt to manually route them, initially) until you are satisfied with the final result.

Your final layout will look like the one shown in Figure 7. Using Context -> Hierarchy -> Peek Area:, the cell will look like the one shown in Figure 8.

Step 6: Full Layout Verification

The final layout should be checked for design rule violations. This can be done in the same way you checked your cell layout using Check in the ICrules palette with one exception. When you check the entire layout your will find some DRC errors in the pad frame as well as any DRC errors that still exist in the cell layout. The pad frame errors are inconsequential and are results of using an optional set of design rules. Focus on the design rules that exist independent of the pad frame by excluding certain cells from the DRC.

Select Check from the ICrules palette.

Click on options in the resulting prompt bar, and enter the following under “Exclude Cell”: PadOut, PadGnd, PadVdd, PadInC, PadVcc, PadFC, PadSpace, PadBidir (and any other pad names you see in the padframe). If you did a DRC on your core logic, you can also exclude that from the checks. Click OK on options, and OK to start the DRC. You should get the following:

”DRC completed. Total RuleChecks: 80; Total Results 0; Total original geometries 5787; ....”.

Step 7: LVS check

For LVS check of the final layout see the following document:

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Figure 7. Final layout of the integrated circuit.

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Figure 8. Layout of the complete integrated ciruit.

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Preparing Fabrication Data

In order to prepare fabrication data for MOSIS you will need to perform following steps.

Step 1: Invoke the IC station

$ adk_ic &

Step 1: Create a new IC cell

Create a new cell in GE (geometry editing mode). Make sure you specify the correct process and cell.

Step 2: Add the cell completed to this new cell

Use Add->Cell to add the top-level design to this new cell (including wired padframe). Don’t do any editing of the cell at this point.

Step 3: Scale the cell to the correct technology

Use ADK->Scale to select the technology you are targeting. This will be AMI 0.5 micron. This will appropriately scale your design for that technology.

Step 4: Write out GDSII file

To write a GDSII stream use Translate->ICLink. Select the source format as ICgraph and the destination as GDSII. Click OK and another dialog appears that will ask for the source and destination names and option file. Enter the name of your source cell, the destination (extension should be .gdsii) and the option file. For the option file, you should use $ADK/lib/iclink_gdsii.option.

A GDSII file will be produced and that is what you send to MOSIS. This is the file you will be submitting to me, so include your team name if you have one or one of your team members' names, i.e. do not use "project_gds" or "multiplier_gds" because I will not be able to tell which project belongs to which team. Click on OK. The message "Starting conversion" will appear at the bottom of the IC window. After a long period of time, another message will appear saying "ICLink completed with errors." Check either the terminal window you called IC from or the ICLink_log_x file (where x is a number, i.e. 0, 1...) to make sure that there were only warnings and no errors. You can ignore warnings about unplaced objects.

Step 5: Submit the design to instructor

Send me mail giving the full path to the GDSII file, i.e. /home/student/vlsi_genious/mgc/project/genious_lfsr_gdsii. Make sure the file permissions are set so that I can read it, i.e. make sure the file is readable by more than just yourself. Also send me the path to the two LVS reports.

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References:

[1] Designing ASICs with the ADK Design Kit and Mentor Graphics Tools, Version 2.0, Mentor Graphics, 2001



[2] David M. Zar tutorials

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