James Keithan
James Keithan
Design Verification engineer presently planning and implementing SystemVerilog testbenches utilizing Universal Verification Methodology (UVM). Decades of experience architecting and implementing High Level Verification (HLV) testbenches. A proven history of leading teams in architecture, project management, and individual contributor.
Expert in design and verification languages;
□ SystemVerilog [VCS, Incisive & Questa] - architecting UVM, OVM, & VVM
□ System C, C++, e – Specman, Vera, VHDL
Recent Work History:
ALTERA August 2012 – Feb 2013
Designed UVM architecture to verify DSP ASIC for QAM modulation. Implemented all stimulus, drivers, monitors, and scoreboards. Placed heavy use on C, C++ prediction, several routines derived from MatLab models. Mentored junior engineers who contributed modules to effort under my architectural lead.
SEAKR October 2011 – August 2012
Designed OVM architecture verifying Data recorder. Wrote agents for record, play, DRAM storage, and proprietary bus communications. Assisted in scoreboard design and development, working closely to link agents and sequences seamlessly to scoreboard. Modeled register space with OVM base classes, similar to RAL.
Entire testbench is self-checking, responding to any sequences’ stimulus and DUT state.
Also wrote assertions to monitor DRAM cycles and DUT record/play protocol.
DEShaw Research January 2011 – October 2011
Developing VMM environment for Multi-Processor design. Architected data transfer and translation between several bus protocols including PCIe. Utilized high level of abstraction test objects – multi stream scenarios, type factories, and distributed prediction.
IronKey September 2010 - December 2010
Developing OVM environment for secure NAND flash device. Large FPGA with embedded ARM processor, encryption, and caching. Exercised device with OVM virtual sequences and C-model prediction through DPI interface. Also extensive work in PERL to create an automated register set description for all blocks, as well as html documentation. All under subversion revision control.
Seagate March 2010 - September 2010
Design Verification consultant for Host to Solid State Drive (SSD) data transfer ASIC. Using Synopsys VMM 1.2 methodology to design and build reusable templated testbench for several modules and mega-blocks. Architected methodology and testing flow. Wrote host (SATA/SAS) interface model as well as AHB model. VMM is essentially aligned with OVM now – with the additions of useful verification blocks.
LSI December 2009 - March 2010
Design Verification consultant verifying L3 Cache controller to IBM PLB6 on chip system bus. I was brought in to quickly fill a gap in testbench development – the scoreboard. Came up to speed quickly, utilized VMM data stream scoreboard and other VMM library elements to deliver scoreboard on schedule. True reuse of verification component was achieved through VMM system of class inheritance and callback technology.
Netronome Systems August 2008 - December 2009
Senior Design Verification engineer position. Verified network processor core(s) and cryptography unit in OVM/Incisive. Unique internal processor bus design, large memory array, programmable (firmware) cryptography cores. Results prediction required DPI to C++ interface and function calls. Crypto was first unit fully verified however company ran out of funding and laid off most of engineering staff.
Mentor Graphics January 2006 - August 2008
Staff Design Verification engineer specializing in Pre-synthesis design verification. Work focuses on new Hardware Verification Languages (HVLs) and teaching Object Oriented Programming (OOP) techniques. Architected System Verilog verification system for major Military/Aerospace Corporation using AVM, now OVM. This included training engineers, documenting existing and proposed testbench architecture, and implemented key parts. Earned engagement of the year award in first year of employment for constant dedication to customers’ needs.
Hamilton Sundstrand – United Technologies February 2005 - January 2006
Consultant - VHDL based verification of flight critical FPGA designs. Wrote VHDL tests for jet engine fuel control designs. Introduced advanced techniques to existing directed test environment. Modeled surrounding system, used random generation, and automated checking. This effort reduced lab debug time significantly.
Intel Corporation March 2004 - February 2005
Consultant - writing e (Specman) tests. Designed and implemented PCI-express model. Participated in verification committee writing an Intel verification techniques manual.
Synopsys January 2002 - March 2004
Recruited to build design verification consulting service at Synopsys. Wrote Vera testbench “Quick Start” training. Later deployed as part of methodology team to DSP consortium as verification lead. Team was tasked to design an entire flow from RTL to layout. It also had to fit into both major contributors’ technology.
Verisity Design April 1997 - December 2001
First Applications Engineer hired in U.S. for Verisity. Delivered Sales presentations, answered support calls, wrote device models. Territory was eastern U.S. and Canada. Awarded AE of the year in Verisity’s first year in existence.
Publications
Compressing Scoreboards Utilizing the VMM Data Stream Scoreboard– SNUG 2010
Finding the Flow : Planning Verification Environments – CDNLive 2009
The Use of Advanced Verification Methods to Address DO-254 Design Assurance
– 2008 IEEE Aerospace Conference
Deliberate Verification Using Random Techniques – MARLUG 2006
Awards
Engagement of the year - Mentor 2006
AE of the year - Verisity 1997
Honor man – USN/AFTA training
Military Service
Unites Stated Marine Corps
Honorable discharge
Education
University of Connecticut 1987
AVA/AFTA USN Avionics school
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