ANAND INSTITUTE OF HIGHER TECHNOLOGY



CS 2253 COMPUTER ORGANIZATION AND ARCHITECTURE 3 0 0 3

(Common to CSE & IT)

1. BASIC STRUCTURE OF COMPUTERS 9

Functional units – Basic operational concepts – Bus structures – Performance and metrics – Instructions and instruction sequencing – Hardware – Software Interface – Instruction set architecture – Addressing modes – RISC – CISC. ALU design – Fixed point and floating point operations.

2. BASIC PROCESSING UNIT 9

Fundamental concepts – Execution of a complete instruction – Multiple bus organization – Hardwired control – Micro programmed control – Nano programming.

3. PIPELINING 9

Basic concepts – Data hazards – Instruction hazards – Influence on instruction sets – Data path and control considerations – Performance considerations – Exception handling.

4. MEMORY SYSTEM 9

Basic concepts – Semiconductor RAM – ROM – Speed – Size and cost – Cache memories – Improving cache performance – Virtual memory – Memory management requirements – Associative memories – Secondary storage devices.

5. I/O ORGANIZATION 9

Accessing I/O devices – Programmed Input/Output -Interrupts – Direct Memory Access – Buses – Interface circuits – Standard I/O Interfaces (PCI, SCSI, USB), I/O devices and processors.

TOTAL = 45

Text Book:

1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, “Computer Organization”, Fifth Edition, Tata McGraw Hill, 2002.

References:

1. David A. Patterson and John L. Hennessy, “Computer Organization and Design: The Hardware/Software interface”, Third Edition, Elsevier, 2005.

2. William Stallings, “Computer Organization and Architecture – Designing for Performance”, Sixth Edition, Pearson Education, 2003.

3. John P. Hayes, “Computer Architecture and Organization”, Third Edition, Tata McGraw Hill, 1998.

4. V.P. Heuring, H.F. Jordan, “Computer Systems Design and Architecture”, Second Edition, Pearson Education, 2004.

ANAND INSTITUTE OF HIGHER TECHNOLOGY

KAZHIPATTUR

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

EVEN SEMESTER

QUESTION BANK

SUBJECT CODE/ NAME: CS 2253/COMPUTER ORGANIZATION AND ARCHITECTURE

STAFF NAME: MR.A.S.BALAJI YEAR/SEMESTER: II/IV/A & B

TWO MARK QUESTIONS AND ANSWERS

UNIT-I

BASIC STRUCTURE OF COMPUTERS

1.Define Computer Architecture

Computer Architecture Is Defined As The Functional Operation Of The Individual H/W Unit In A Computer System And The Flow Of Information Among The Control Of Those Units.

2.Define Computer H/W

Computer H/W Is The Electronic Circuit And Electro Mechanical Equipment That

Constitutes The Computer

3. What are the functions of control unit ?

The memory arithmetic and logic ,and input and output units store and process information and perform i/p and o/p operation, the operation of these unit must be co ordinate in some way this is the task of control unit the cu is effectively the nerve center that sends the control signal to other units and sence their states.

4.What is an interrupt?

An interrupt is an event that causes the execution of one program to be suspended and

another program to be executed.

5. What are the uses of interrupts?

• Recovery from errors

• Debugging

• Communication between programs

• Use of interrupts in operating system

6.What is the need for reduced instruction chip?

• Relatively few instruction types and addressing modes.

• Fixed and easily decoded instruction formats.

• Fast single-cycle instruction execution.

• Hardwired rather than microprogrammed control.

7. Name any three of the standard I/O interface.

• SCSI (small computer system interface),bus standards

• Back plane bus standards

• IEEE 796 bus (multibus signals)

• NUBUS

• IEEE 488 bus standard

8. Differentiate between RISC and CISC

|RISC |CISC |

|Reduced Instruction Set Computer |1. Complex Instruction set computer |

|Simple instructions take one cycle per |Complex instruction take multiple |

|Operation |Cycles per operation. |

|Few instructions and address modes areUsed. |Many instruction and address |

| |Modes. |

|Fixed format instructions are used. |Variable format instructions are used |

|Instructions are compiled and then executed by hardware. |Instructions are interpreted by the |

| |Microprogram and then executed. |

|RISC machines are multiple registerset. |CISC machines use single registerSet. |

|Complexity in the compiler |Complexity in the microprogram |

|RISC machines are higly piplined |CISC machines are not piplined. |

9. Explain the various classifications of parallel structures.

• SISD (single instruction stream single data stream

• SIMD(single instruction stream multiple data stream

• MIMD(multiple instruction stream multiple data stream

• MISD(multiple instruction stream single data stream

10. What is absolute addressing mode?

The address of the location of the operand is given explicitly as a part of the instruction.

Eg. Move a , 2000

11. Specify three types of data transfer techniques.

• Arithmetic data transfer

• Logical data transfer

• Programmed control data transfer

12. What is the role of MAR and MDR?

The MAR (memory address register) is used to hold the address of the location to or from which data are to be transferred and the MDR(memory data register) contains the data to be written into or read out of the addressed location.

13. What are the various types of operations required for instructions?

• Data transfers between the main memory and the CPU registers

• Arithmetic and logic operation on data

• Program sequencing and control

• I/O transfers

14. What is the role of IR and PC?

Instruction Register (IR) contains the instruction being executed. Its output is availableto the control circuits, which generate the timing signals for controlling the processing circuitsneeded to execute the instructions.The Program Counter (PC) register keeps track of the execution of the program. It contains the memory address of the instruction currently being executed . During the execution of the current instruction, the contents of the PC are updated to correspond to the address of the next instructions to be executed.

15.What are the various units in the computer?

• Input unit

• Output unit

• Control unit

• Memory unit

• Arithmetic and logical unit

16. What is an I/O channel?

An I/O channel is actually a special purpose processor, also called peripheral processor. The main processor initiates a transfer by passing the required information in the input output channel. The channel then takes over and controls the actual transfer of data.

17.What is a bus?

A collection of wires that connects several devices is called a bus.

18.Define word length?

Each group of n bits is referred to as a word of information and n is called the word

length.

19.Explain the following the address instruction?

• Three-address instruction-it can be represented as add a,b,c

Operands a,b are called source operand and c is called destination operand.

• Two-address instruction-it can be represented as Add a,b

• One address instruction-it can be represented as add a

20.Zero address instruction.

It is also possible to use instruction where the location s of all operand are defined implicitly. This operand of the use of the method for storing the operand in which called push down stack. Such instructions are sometimes referred to us zero address instruction.

21.What is the straight-line sequencing?

The CPU control circuitry automatically proceed to fetch and execute instruction, one at

a time in the order of the increasing addresses. This is called straight line sequencing.

22.What is the role of PC?

The CPU contains a register called the program counter, which holds the address of instruction to be executed next to begin the execution of the program the address of its First instruction must be placed into the pc.

23. Define Signal

Signal - The binary information is represented in digital computers by physical quantities

called signals.

24. Define Gates

Gates – The manipulation of binary information is done by logic circuits called gates.

Gates are blocks of hardware that produce signals of binary 1 or 0 where input logic

requirements are satisfied.

25. Flip flop

Flip flop – The storage elements employed in clocked sequential circuits are called flip

flops. A flip flop is a binary cell capable of storing 1 bit of information.

26.State and explain the performance equation?

Suppose that the average number of basic steps needed to execute one machine instruction is S, where each basic step is completed in one clock cycle. If the clock cycle rate is R cycles per second, the program execution time is given by

T = (N x S) / R This is often referred to as the basic performance equation.

27. Define CPI

The term ClockCyclesPerInstructionWhich is the average number of clock cycles each

instruction takes to execute, is often abbreviated as CPI.

CPI= CPU clock cycles/Instruction count.

28. Define MIPS .

MIPS:One alternative to time as the metric is MIPS(Million Instruction Per Second)

MIPS=Instruction count/(Execution time x1000000).

This MIPS measurement is also called Native MIPS todistinguish it from some

alternative definitions of MIPS.

29.Define MIPS Rate:

The rate at which the instructions are executed at a given time.

30.Define Throughput and Throughput rate.

Throughput -The total amount of work done in a given time.

Throughput rate-The rate at which the total amount of work done at a given time.

31. State the principle of operation of a carry look-ahead adder.

The input carry needed by a stage is directly computed from carry signals obtained from all the preceding stages i-1,i-2,…..0, rather than waiting for normal carries to supply slowly from stage to stage. An adder that uses this principle is called carry look-ahead adder.

32. What are the main features of Booth’s algorithm?

1) It handles both positive and negative multipliers uniformly.

2) It achieves some efficiency in the number of addition required when the multiplier has a few large blocks of 1s.

33. How can we speed up the multiplication process?(CSE Nov/Dec 2003)

There are two techniques to speed up the multiplication process:

1) The first technique guarantees that the maximum number of summands that must be added is n/2 for n-bit operands.

2) The second technique reduces the time needed to add the summands.

34. What is bit pair recoding? Give an example.

Bit pair recoding halves the maximum number of summands. Group the Booth-recoded multiplier bits in pairs and observe the following: The pair (+1 -1) is equivalent to the pair (0 +1). That is instead of adding -1 times the multiplicand m at shift position i to +1 ( M at position i+1, the same result is obtained by adding +1 ( M at position i.

Eg: 11010 – Bit Pair recoding value is 0 -1 -2

35. What is the advantage of using Booth algorithm?

1) It handles both positive and negative multiplier uniformly.

2) It achieves efficiency in the number of additions required when the multiplier has

a few large blocks of 1’s.

3) The speed gained by skipping 1’s depends on the data.

36. Write the algorithm for restoring division.

Do the following for n times:

1) Shift A and Q left one binary position.

2) Subtract M and A and place the answer back in A.

3) If the sign of A is 1, set q0 to 0 and add M back to A.

Where A- Accumulator, M- Divisor, Q- Dividend.

37. Write the algorithm for non restoring division.

Do the following for n times:

Step 1: Do the following for n times:

1) If the sign of A is 0 , shift A and Q left one bit position and subtract M from A; otherwise , shift A and Q left and add M to A.

2) Now, if the sign of A is 0,set q0 to 1;otherwise , set q0 to0.

Step 2: if the sign of A is 1, add M to A.

38. When can you say that a number is normalized?

When the decimal point is placed to the right of the first (nonzero) significant digit, the number is said to be normalized.

39. Explain about the special values in floating point numbers.

The end values 0 to 255 of the excess-127 exponent E( are used to represent special values such as:

When E(= 0 and the mantissa fraction M is zero the value exact 0 is represented.

When E(= 255 and M=0, the value ( is represented.

When E(= 0 and M (0 , denormal values are represented.

When E(= 2555 and M(0, the value represented is called Not a number.

40. Write the Add/subtract rule for floating point numbers.

1) Choose the number with the smaller exponent and shift its mantissa right a number of steps equal to the difference in exponents.

2) Set the exponent of the result equal to the larger exponent.

3) Perform addition/subtraction on the mantissa and determine the sign of the result

4) Normalize the resulting value, if necessary.

41. Write the multiply rule for floating point numbers.

1) Add the exponent and subtract 127.

2) Multiply the mantissa and determine the sign of the result .

3) Normalize the resulting value , if necessary.

42. What is the purpose of guard bits used in floating point arithmetic

Although the mantissa of initial operands are limited to 24 bits, it is important to retain extra bits, called as guard bits.

43. What are the ways to truncate the guard bits?

There are several ways to truncate the guard bits:

1) Chooping

2) Von Neumann rounding

3) Rounding

44. Define carry save addition(CSA) process.

Instead of letting the carries ripple along the rows, they can be saved and introduced into the next roe at the correct weighted position. Delay in CSA is less than delay through the ripple carry adder.

45. What are generate and propagate function?

The generate function is given by

Gi=xiyi and

The propagate function is given as

Pi=xi+yi.

46. What is floating point numbers?

In some cases, the binary point is variable and is automatically adjusted as computation proceeds. In such case, the binary point is said to float and the numbers are called floating point numbers.

47. In floating point numbers when so you say that an underflow or overflow has occurred?

In single precision numbers when an exponent is less than -126 then we say that an underflow has occurred. In single precision numbers when an exponent is less than +127 then we say that an overflow has occurred.

48. What are the difficulties faced when we use floating point arithmetic?

Mantissa overflow: The addition of two mantissas of the same sign may result in a carryout of the most significant bit

Mantissa underflow: In the process of aligning mantissas ,digits may flow off the right end of the mantissa.

Exponent overflow: Exponent overflow occurs when a positive exponent exceeds the maximum possible value.

Exponent underflow: It occurs when a negative exponent exceeds the maximum possible exponent value.

49.In conforming to the IEEE standard mention any four situations under which a processor sets exception flag.

Underflow: If the number requires an exponent less than -126 or in a double precision, if the number requires an exponent less than -1022 to represent its normalized form the underflow occurs.

Overflow: In a single precision, if the number requires an exponent greater than -127 or in a double precision, if the number requires an exponent greater than +1023 to represent its normalized form the underflow occurs.

Divide by zero: It occurs when any number is divided by zero.

Invalid: It occurs if operations such as 0/0 are attempted.

50. Why floating point number is more difficult to represent and process than integer?(CSE May/June 2007)

An integer value requires only half the memory space as an equivalent.IEEEdouble-precision floatingpoint value. Applications that use only integer based arithmetic will therefore also have significantly smaller memory requirement

A floating-point operation usually runs hundreds of times slower than an equivalent integer based arithmetic operation.

51.Give the booth’s recoding and bit-pair recoding of the computer.

1000111101000101(CSE May/June 2006)

Booth’s recoding

1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0

-1 0 0 +1 0 0 0 -1 +1 -1 0 0 +1 -1 +1 -1

Bit-Pair recoding:

1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0

-2 +1 0 -1 +1 0 +1 1

52.Draw the full adder circuit and give the truth table (CSE May/June 2007)

|Inputs |Outputs |

|A |B |C |Carry |Sum |

|0 |0 |0 |0 |0 |

|0 |0 |1 |0 |1 |

|0 |1 |0 |0 |1 |

|0 |1 |1 |1 |0 |

|1 |0 |0 |0 |1 |

|1 |0 |1 |1 |0 |

|1 |1 |0 |1 |0 |

|1 |1 |1 |1 |1 |

UNIT-II

BASIC PROCESSING UNIT

1.Specify the sequence of operation involved when an instruction is executed.

a)Instruction Fetch

b)Instruction Decode

c)Operand Fetch

d)Execute

e) Write Back

2.Define parallel processing.

Parallel processing is a term used to denote a large class of techniques that are used to provide simultaneous data-processing tasks for the purpose of increasing the computational speed of a computer system. Instead of processing each instruction sequentially as in a conventional computer, a parallel processing system is able to perform concurrent data

processing to achieve faster execution time.

3. Define sequential circuits.

A sequential circuit is an interconnection of flip-flops and gates. The gates by themselves constitute a combinational circuit, but when included with the flip flops, the overall circuit is classified as a sequential circuit.

4.Define interface.

The word interface refers to the boundary between two circuits or devices

5.Define processor clock.

Processor clock: Processor circuits are controlled by a timing signal called processor

clock, the clock defines regular time interval called clock cycle.

6. Define latency.

The term memory latency is used to refer to the amount of time it takes to transfer a word of data to or from the memory. The term latency is used to denote the time it takes to transfer the first word of data. This time is usually substantially longer than the time needed to transfer each subsequent word of a block.

7. Define bandwidth.

Bandwidth is a product of the rate at which the data are transferred (and accessed) and

the width of the data bus.

8. Define hit rate.

A successful access to data in a cache is called a hit. Number of hits stated as a fraction

of all attempted accesses is called the hit rate.

9. Define miss rate.

A miss rate is the number of misses stated as a fraction of attempted accesses. Extra time needed to bring the desired information into the cache is called the miss penalty.

10.Define Clock Rate:

Clock rate, R=1/p cycles/sec(hz)

Where p is length of one clock cycle

11.Define Throughput:

The total amount of work done in a given time

12.Different types of buses.

1.Synchronous bus

2.Asynchronous bus

13. What is micro programming and micro programmed control unit?

Microprogramming is a method of control unit design in which the control unit selection and sequencing information are stored in ROM and RAM’s called control store or control memory. Micro programmed control unit is a general approach used for implementation of control unit. Here control signals are generated by a program similar to machine language Programs

14. What is meant by hardwired control?

It is the one that contains control units that use fixed logic circuits to interpret instructions

and generate control signals from them. Here,the fixed logic circuit block includes combinational

circuit that generates the required control outputs for decoding and encoding functions.

15. What is Register Renaming?

If a temporary register assumes the role of the permanent register whose data it is holding and is given the same name is called as the Register Renaming.

16. What is the function of commitment unit?

When out-of-order execution is allowed, a s pecial control unit called as “commitment unit” is used to guarantee in-order commitment. It uses a queue called the “reorder buffer” to determine which instruction should be committed next. This is the function of commitment unit.

17. What is the neccesity of grouping signals?

It is used to reduce the number of the bits in the microinstruction.It is used to overcome the draw back of assigning individual bits to each control signal results in long microinstructions, because the number of the required signals is usually large, moreover only a few bits are used in any given instruction.

18.List the techniques used for grouping of the control signals?

a) Vertical organization

b) Horizontal organization

19 List out Various branching technique used in micro program control unit?

a) Bit-Oring

b) Using Conditional Variable

c) Wide Branch Addressing

20. Define the term Clock Rate.

They are two possibilities for increasing the clock rate, R. First, improving the IC technology makes logic circuits faster, which reduces the time needed to complete a basic step. This allows the clock period P to be reduce and the clock rate R to be increased Second, reducing the amount of processing done is one basic step makes it possible to reduce the clock period P. 21. What do you mean by out-of order execution? Is it Desirable?

In a pipelined processor with several instructions is process concurrently it is Possible for instruction to finish out of sequence, one instruction finishes before Another which is issued earlier, as far as main computation is concerned no Hazards will happen but if an interrupts occurs it creates the problem.

22. Define Overflow

Overflow -In the single precision, if the number requires a exponent greater then +127

or in a double precision, if the number requires an exponent form the overflow occurs.

23.Define Underflow

Underflow-In a single precision ,if the number requires an exponent less than -26 or in a double precision, if the number requires an exponent less than -1022 to represent its normalized form the underflow occurs.

24. What are Condition Codes (CC)? Explain the use of them.

Condition Codes are the list of possible conditions that can be tested during conditional is used to test the condition (). Based on this result, Jump instructions move to specified flags represent the value of processor that keeps the information about the results of various operations for use by conditional branches.

25. What is straight –line sequencing?

Process of fetching and executing an instruction; one at a time in order of increasing address with the help of information in program counter.

UNIT-III

PIPELINING

1.Define pipelining.

Pipelining is a technique of decomposing a sequential process into sub operations with each sub process being executed in a special dedicated segment that operates concurrently with all other segments.

2.Define parallel processing.

Parallel processing is a term used to denote a large class of techniques that are used to provide simultaneous data-processing tasks for the purpose of increasing the computational speed of a computer system. Instead of processing each instruction sequentially as in a conventional computer, a parallel processing system is able to perform concurrent data

processing to achieve faster execution time.

3.Define instruction pipeline.

The transfer of instructions through various stages of the CPU instruction cycle.,including fetch opcode, decode opcode, compute operand addresses. Fetch operands, execute Instructions and store results. This amounts to realizing most (or) all of the CPU in the form of multifunction pipeline called an instruction pipelining.

4. What are the steps required for a pipelinened processor to process the instruction?

• F Fetch: read the instruction from the memory

• D Decode: decode the instruction and fetch the source operand(s).

• E Execute: perform the operation specified by the instruction.

• W Write: store the result in the destination location

5. What are Hazards?

A hazard is also called as hurdle .The situation that prevents the next instruction in the instruction stream from executing during its designated Clock cycle. Stall is introduced by hazard. (Ideal stage)

6. State different types of hazards that can occur in pipeline.

The types of hazards that can occur in the pipelining were,

1. Data hazards.

2. Instruction hazards.

3. Structural hazards.

7. Define Data hazards

A data hazard is any condition in which either the source or the destination operands of

an instruction are not available at the time expected in pipeline. As a result some operation has

to be delayed, and the pipeline stalls.

8. Define Instruction hazards

The pipeline may be stalled because of a delay in the availability of an instruction. For

example, this may be a result of miss in cache, requiring the instruction to be fetched from the

main memory. Such hazards are called as Instruction hazards or Control hazards.

9.Define Structural hazards?

The structural hazards is the situation when two instructions require the use of a given

hardware resource at the same time. The most common case in which this hazard may arise is

access to memory.

10. What are the classification of data hazards?

Classification of data hazard: A pair of instructions can produce data hazard by referring

reading or writing the same memory location. Assume that i is executed before J. So, the hazards

can be classified as,

1. RAW hazard

2. WAW hazard

3. WAR hazard

11.Define RAW hazard : ( read after write)

Instruction ‘j’ tries to read a source operand before instruction ‘i’ writes it.

12. Define WAW hazard :( write after write)

Instruction ‘j’ tries to write a source operand before instruction ‘i’ writes it.

13.Define WAR hazard :( write after read)

Instruction ‘j’ tries to write a source operand before instruction ‘i’ reads it.

14. How data hazard can be prevented in pipelining?

Data hazards in the instruction pipelining can prevented by the following techniques.

a)Operand Forwarding

b)Software Approach

15.How Compiler is used in Pipelining?

A compiler translates a high level language program into a sequence of machine instructions. To reduce N, we need to have suitable machine instruction set and a compiler that makes good use of it. An optimizing compiler takes advantages of various features of the target processor to reduce the product N*S, which is the total number of clock cycles needed to execute a program. The number of cycles is dependent not only on the choice of instruction, but also on the order in which they appear in the program. The compiler may rearrange program instruction to achieve better performance of course, such changes must not affect of the result of the computation.

16. How addressing modes affect the instruction pipelining?

Degradation of performance is an instruction pipeline may be due to address dependency where operand address cannot be calculated without available informatition needed by addressing mode for e.g. An instructions with register indirect mode cannot proceed to fetch the operand if the previous instructions is loading the address into the register. Hence operand access is delayed degrading the performance of pipeline.

17. What is locality of reference?

Many instruction in localized area of the program are executed repeatedly during some time period and the remainder of the program is accessed relatively infrequently .this is referred as locality of reference.

18. What is the need for reduced instruction chip?

• Relatively few instruction types and addressing modes.

• Fixed and easily decoded instruction formats.

• Fast single-cycle instruction execution.

• Hardwired rather than micro programmed control

19. Define memory access time?

The time that elapses between the initiation of an operation and completion of that operation ,for example ,the time between the READ and the MFC signals .This is Referred to as memory access time.

20. Define memory cycle time.

The minimum time delay required between the initiations of two successive memory operations, for example, the time between two successive READ operations.

21.Define Static Memories.

Memories that consist of circuits capable of retaining the state as long as power is applied are known as static memories.

22. List out Various branching technique used in micro program control unit?

a) Bit-Oring

b) Using Conditional Variable

c) Wide Branch Addressing

23. How the interrupt is handled during exception?

* CPU identifies source of interrupt

* CPU obtains memory address of interrupt handles

* pc and other CPU status information are saved

* Pc is loaded with address of interrupt handler and handling program to handle it.

24. List out the methods used to improve system performance.

The methods used to improve system performance are

1. Processor clock

2.Basic Performance Equation

3.Pipelining

4.Clock rate

5.Instruction set

piler

25. What is DMA?

A special control unit may be provided to enable transfer a block of data directly between

an external device and memory without contiguous intervention by the CPU. This approach is called DMA.

UNIT-IV

MEMORY SYSTEM

1.Give the classification of the Optical Media

Optical media can be classified as

CD-ROM – Compact Disk Read Only Memory

WORM – Write Once Read Many

Rewriteable - Erasable

Multifunction – WORM and Erasable

2. What is a Mini Disk?

Minidisk for data (MD-Data) is the data version of the new rewriteable storage format developed by Sony Corporation for both business and entertainment as a convenient medium for carrying music , video and data. MD can be used in three formats to support all potential uses as follows:

--A premastered optical disk

--A recordable magneto-optical disk

--A hybrid that is partially mastered and partially recordable

3. List some applications for WORM.

--Some of the application or WORM devices are

--On-Line catalogs such as automobile party’s dealer

--Large Volume Distribution

--Transaction logging such as stock trading company

--Multimedia Archival

4. What are multifunctional drives

A multifunctional drive is a single unit which is capable of reading and writing a variety of disk media. This type of drive provides the permanence of a read-only device as well as full flexibility of a rewriteable device along with the powerful intermediate write once capability

5. What are types of technology used in s multifunctional drive?

Three types of technologies utilized for multifunctional drives are

*Magneto – Optical Disk for both rewriteable and WORM capability

*Magneto- Optical disk for rewriteable and dye polymer disk for WORM capability

*Phase change technology for both rewriteable and WORM capability

6. What is Migration and Archiving?

The process of moving an object from one level in the storage hierarchy to another level in that hierarchy is called migration. Migration of Objects to off-line media and removal of these objects from on-line media is called archiving.

7. How do we use a jukebox?

A juke box is used for storing large volumes of multimedia information in one cost effective store . Jukebox – based optical disk libraries can be networked so that multiple users can access the information. Opticla disk libraries serve as nearline storage for infrequently used data.

8. List a few requirements imposed by advanced multimedia applications

Some of the requirements imposed by multimedia application are

*Support for windows – based GUI, such as Microsoft Windows

*Capability to run applications in Multitasking environments

*Support for Multi – User Applications

*Network – bases client –server distributed applications

9. What is the use of High water marks in a cache?

Cache design use a high-water mark and a low water mark to trigger cache management operations. When the cache storage fiklls up to the high – water mark , the cache manager starts creating more space in cache storage. Space is created by discarding objects that have not been modified and writing back those object that have been modified.

10. What are the various cache usage in a LAN –based system?

In a LAN – based system there can be as many as three stages of caches as follows

1. Disk Cache or System memory cache

2. Hard Disk cache for each object server

3. Shared network cache for all object servers

11. What are the multimedia applications which use caches?

Some Multimedia application areas where cache is extensively used are

*Multimedia Entertainment

*Education

*Office Systems

*Audio and video Mail

*Computer Architecture - Set 6

12. Explain virtual memory technique.

Techniques that automatically move program and data blocks into the physical memory

when they are required for execution are called virtual memory technique

13. What are virtual and logical addresses?

The binary addresses that the processor issues for either instruction or data are called

virtual or logical addresses.

14. Define translation buffer.

Most commercial virtual memory systems incorporate a mechanism that can avoid the bulk of the main memory access called for by the virtual to physical addresses translation buffer. This may be done with a cache memory called a translation buffer.

15. What is branch delay slot?

The location containing an instruction that may be fetched and then discarded because of

the branch is called branch delay slot.

16. What is optical memory?

Optical or light based techniques for data storage, such memories usually employ optical

disk which resemble magnetic disk in that they store binary information in concentric tracks on

an electromechanically rotated disks. The information is read as or written optically, however

with a laser replacing the read write arm of a magnetic disk drive. Optical memory offer high

storage capacities but their access rate is are generally less than those of magnetic disk.

17. What are static and dynamic memories?

Static memory are memories which require periodic no refreshing. Dynamic memories

are memories, which require periodic refreshing.

18. What are the components of memory management unit?

A facility for dynamic storage relocation that maps logical memory references into

physical memory addresses.

A provision for sharing common programs stored in memory by different users .

19. What is the role of MAR and MDR?

The MAR (memory address register) is used to hold the address of the location to or from

which data are to be transferred and the MDR(memory data register) contains the data to be

written into or read out of the addressed location.

20. Distinguish Between Static RAM and Dynamic RAM?

Static RAM are fast, but they come at high cost because their cells require several

transistors. Less expensive RAM can be implemented if simpler cells are used. However such

cells do not retain their state indefinitely; Hence they are called Dynamic RAM.

21. Distiguish between asynchronies DRAM and synchronous RAM.

The specialized memory controller circuit provides the necessary control signals, RAS

And CAS ,that govern the timing. The processor must take into account the delay in the response

of the memory. Such memories are referred to as asynchronous DRAMS.The DRAM whose

operations is directly synchronized with a clock signal. Such Memories are known as

synchronous DRAM.

22. What do you mean associative mapping technique?

The tag of an address received from the CPU is compared to the tag bits of each block of the cache to see if the desired block is present. This is called associative mapping technique.

23. What is SCSI?

Small computer system interface can be used for all kinds of devices including RAID

storage subsystems and optical disks for large- volume storage applications.

24. What are the two types of latencies associated with storage?

The latency associated with storage is divided into 2 categories

1. Seek Latencies which can be classified into Overlapped seek,Mid transfer seek and Elevator seek

2. Rotational Latencies which can be reduced either by Zero latency read or Write and Interleave factor.

25. What are the data management activities involved in a storage?

a. Command queuing : allows execution of multiple sequential commands with system

CPU intervention. It helps in minimizing head switching and disk rotational latency

b. Scatter – gather : Scatter is a process whereby data is set for best fit in available

block of memory or disk. Gather reassembles data into contiguous blocks on disk or in memory

27. What do you mean by Disk Spanning?

Disk spanning is a method of attaching drives to a single host uadapter. All drives appear as a single contiguous logical unit. Data is written to the first drive first and when the drive is full, the controller switches to the second drive, then the second drive writes until its full.

28. List some objectives for using RAID Systems

-RAID systems are used to meet the following objectives

-Hot backup of disk systems

-Large volume storage at lower cost

-Higher performance at lower cost

-Ease of data recovery

-High MTBF

29. What are the different levels RAID?

There are six discrete levels of RIAD functionality. They are

-Level 0 – Disk Striping

-Level 1 – Disk Mirroring

-Level 2 – Bit Interleaving of Data

-Level 3 – Bit Interleaving with dedicated parity drives

- Level 4 – Sector interleaving of data with dedicated parity drive

-Level 5 – Block interleaving of data.

30.Two Types of storage devices.

1.Primary Memory

2.Secondary Memory

UNIT-V

I/O ORGANIZATION

1.Explain very briefly about ESDI Hard Drive

ESDI stands for enhanced small device interface was developed by a consortium of several manufacturers. ESDI converts the data into serial bit streams and uses the RLL encoding cheme to pack more bits per sector. ESDI drives store a defect map containing the locations of bad and defective sectors on the drive.

2. Explain in brief about IDE

Integrated device electronics contains an integrated controller with the drive as a single unit. Interface is a simple 16-bit parallel data interface and requires the data to be written and does not need to be told where and how to write the data on the disk. .IDE Interface supports 2 drives – one drive has to be configured as the master and the second as the slave.

3. What is SCSI?

Small computer system interface can be used for all kinds of devices including RAID storage subsystems and optical disks for large- volume storage applications.

4. Define the term RELIABILITY

“Means feature that help to avoid and detect such faults. A realible system does not silently continue and delivery result that include interrected and corrupted data, instead it corrects the corruption when possible or else stops

5.Define the term AVAILABLITY:

“Means features that follow the systerm to stay operational even offen faults do occur. A highly available systerm could dis able do the main functioning portion and continue operating at the reduced capacity”

6. How the interrupt is handled during exception?

* cpu identifies source of interrupt

* cpu obtains memory address of interrupt handles

* pc and other cpu status information are saved

* Pc is loaded with address of interrupt handler and handling program to handle it

7. What is IO mapped input output?

A memory reference instruction activated the READ M (or)WRITE M control line and does not affect the IO device. Separate IO instruction are required to activate the READ IO and WRITE IO lines ,which cause a word to be transferred between the address aio port and the CPU. The memory and IO address space are kept separate.

8.Specify the three types of the DMA transfer techniques?

--Single transfer mode(cyclestealing mode)

--Block Transfer Mode(Brust Mode)

--Demand Transfer Mode

--Cascade Mode

9. What is an interrupt?

An interrupt is an event that causes the execution of one program to be suspended and another program to be executed.

10.What are the uses of interrupts?

*Recovery from errors

*Debugging

*Communication between programs

*Use of interrupts in operating system

11.Define vectored interrupts.

In order to reduce the overhead involved in the polling process, a device requesting an interrupt may identify itself directly to the CPU. Then, the CPU can immediately start executing the corresponding interrupt-service routine. The term vectored interrupts refers to all interrupthandling schemes base on this approach.

12. Name any three of the standard I/O interface.

*SCSI (small computer system interface),bus standards

*Back plane bus standards

*IEEE 796 bus (multibus signals)

*NUBUS & IEEE 488 bus standard

13. What is an I/O channel?

An i/o channel is actually a special purpose processor, also called peripheral processor.The main processor initiates a transfer by passing the required information in the input output channel. the channel then takes over and controls the actual transfer of data.

14.What is a bus?

A collection of wires that connects several devices is called a bus.

15.Define word length?

Each group of n bits is referred to as a word of information and n is called the word length.

16. Why program controlled I/O is unsuitable for high-speed data transfer?

In program controlled i/o considerable overhead is incurred..because several program instruction have to be executed for each data word transferred between the external devices and MM.Many high speed peripheral; devices have a synchronous modes of operation.that is data transfer are controlled by a clock of fixed frequency, independent of the cpu.

17.what is the function of i/o interface?

The function is to coordinate the transfer of data between the cpu and external devices.

18.what is NUBUS?

A NUBUS is a processor independent, synchronous bus standard intended for use in 32 bitmicro processor system. It defines a backplane into which upto 16 devices may be plugged each in the form of circuit board of standard dimensions.

19. Name some of the IO devices.

*Video terminals

*Video displays

*Alphanumeric displays

*Graphics displays

* Flat panel displays

*Printers

*Plotters

20. What are the steps taken when an interrupt occurs?

*Source of the interrupt

*The memory address of the required ISP

* The program counter &cpu information saved in subroutine

*Transfer control back to the interrupted program

21.Define interface.

The word interface refers to the boundary between two circuits or devices

22.What is programmed I/O?

Data transfer to and from peripherals may be handled using this mode. Programmed I/O

operations are the result of I/O instructions written in the computer program.

23.Types of buses.

-Synchronous bus

-Asynchronous bus

24.Define Synchronous bus.

- Synchronous bus on other hand contains synchronous clock that is used to validate each and every signal.

- Synchronous buses are affected noise only when clock signal occurs.

- Synchronous bus designers must control with meta stability when attempting different clock signal Frequencies

- Synchronous bus of meta stability arises in any flip flop. when time will be violated.

25. Define Asynchronous bus.

- Asynchronous buses can mistake noise pulses at any time for valid handshake signal.

- Asynchronous bus designer must deal with events that like synchronously.

- It must contend with meta stability when events that drive bus transaction.

-When flip flop experiences effects can occur in downstream circuitry unless proper design technique which are used

16 MARK QUESTIONS

UNIT-1

1.Draw and explain the block diagram of a simple computer with five functional units.

2.What is RISC ?Explain with proper example.

3. What is CISC ?Explain with proper example.

4.What are the techniques used to measure the performance of a computer?

5.What do you mean by addressing modes? Explain various addressing modes with the help of

examples.

UNIT-2

1. a)How will you perform arithmetic or logic operation?

b)How to fetch a word from memory and store a word in memory?

2. What is meant by hardwired control? Draw and explain typical hardwire control unit.

3. What is meant by microprogramming? Draw and explain the micro programmed control unit.

4. List the advantages and disadvantages of micro programmed control unit over hardwire

control unit.

5. Explain in detail about nano programming and list out its benefits.

UNIT-3

1.State and explain the different types of hazards that can occur in a pipeline.

2.Draw and explain the structure of a superscalar processor. Also explain the flow of instruction

execution in it.

3.what are the two aspects of machine instruction? Explain it .

4.Draw and explain the modified three-bus structure of the processor suitable for four -stage

pipelined execution. How this structure is suitable to provide four-stage pipelined execution?

UNIT-4

1.Define cache memory. Explain the mapping process followed in cache memory. Also discuss

the relative advantages and disadvantages of the mapping techniques used.

2.What is virtual memory? Why is it necessary to implement virtual memory? Explain the virtual

memory address translation.

3.Draw and explain the various types of secondary storage devices.

4.a)Explain about RAM.

b)Explain about ROM.

UNIT-5

1.List the different types of interrupts. Explain briefly about mask able interrupt.

2.What is DMA? Explain the block diagram of DMA .Also describe how DMA is used to

transfer data from peripherals.

3.Explain the features of USB,PCI,SCSI bus.

UNIVERSITY QUESTIONS YEAR WISE

SUBJECT CODE/ NAME: CS 2253/COMPUTER ORGANIZATION AND ARCHITECTURE

UNIT I

2 Marks

1. What is register indirect addressing mode? When is it used? (Nov/Dec2013)

2. Differentiate between RISC and CISC. (Nov/Dec2013)

3. What is meant by an addressing mode?Mention most important of them. May/June(2013)

4. State the rule for floating point addition. May/June(2013)

5. What is SPEC?Specify the formula for SPEC rating. May/June(2012)

6. What is relative addressing mode?When is it used? May/June(2012)

7. What is an opcode? How many bits are needed to specify 32 distinct operations? May(2011)

8. Write the logic equations of a binary half adder. May(2011)

9. Compare RISC and CISC architecture?(may ’10)

10. What are the types of CPU organization?(Nov 2010)

11. What are the diff types of address instructions?Give example?(Nov 2010)

12. What does the term hertz refer to? (Nov/Dec2010)

13. How is the number 25 represented in BCD and ASCII code? (Nov/Dec2010)

14. Distinguish between autoincrement and autodecrement addressing mode?(may ’10)

15. What are tri-state gate?May(2008)

16. Why is the data bus in most microprocessors bidirectional while the address bus is unidirectional? May(2008),(May 2007)

17. Perform 1010100-1000100 using 1’s complement and 2’s complement? may(2008)

18. Define unterflow and Overflow? May(2008)

19. A memory byte location contain the pattern 00101100.What does this pattern represent when interpreted as a number? What does it represent as an ASCII Code?(Nov,07)

20. What is the information conveyed by addressing modes? (Nov,07)

21. Draw the full adder circuit using two half adders? (Nov,07)

22. What are the various ways of representing signed integers in the system? (Nov,07)

23. What are limitations of assembley language?(May 07)

24. Why floating point number is more difficult to represent and process than integer? (May 07)

25. Draw a full adder circuit and give truth table? (May 07)

UNIT I

16 Marks

1. Explain in detail the different instruction formats with examples.(8) (Nov/Dec2013)

2. Explain ALU design.(8) (Nov/Dec2013)

3. Explain instruction sequencing in detail.(10) (Nov/Dec2013)

4. What is the need for addressing modes?Explain any two types of addressing modes with examples.(6) (Nov/Dec2013)

5. Explain different types of instructions with pare their relative merits and demerits.(8) May/June(2013)

6. Explain with an example how to multiply two unsigned binary numbers.(8) May/June(2013)

7. Explain the design of ALU in detail.(16) May/June(2013)

8. What are addressing modes? Explain the various addressing modes with examples. May/June(2012)

9. Derive and explain an algorithm for adding and subtracting two floating point binary numbers. May/June(2012)

10. Explain instruction sequencing in detail. May/June(2012)

11. Differentiate RISC and CISC architectures. May/June(2012)

12. With examples explain the Data transfer, Logic and Program Control Instructions? (16)May(2011)

13. Explain the Working of a Carry-Look Ahead adder. (16) May(2011)

14. Describe the connection between the processor and memory with a neat structure diagram. (Nov 2010)

15. Explain how the expression X=A X B + C X C will be executed in one address,two address and three address processors in an accumulator organization. ?(Nov 2010)

16. Explain in detail how Instructions arre encoded? ?(Nov 2010)

17. Draw the diagram of a carry look ahead adder and explain the carry look-ahead principle? (Nov 2010)

18. Describe in detail booth’s multiplication algorithm and its hardware implementation? (Nov 2010)

19. Explain the architecture of basic computer with neat diagram? ?(Nov 2010)

20. Define addressing mode.Classify addressing modes and explain each type with eg? ?(Nov 2010)

21. Describe the role of system software to improve the performance of a computer?(8) (may ’10)

22. Design a 4-bit adder/subtractor circuit using full adders and explain it’s function? (may ’10)

23. What are the Special registers in a typical computer?Explain their purpose in detail? (may ’10)

24. Design a 4-bit fast adder and explain its function in detail? (may ’10)

25. Explain how the processor is interfaced with the memory with a neat block diagram and explain how they communicate? ?(Nov,07)

26. What do you know about bits,bytes,nibbles, and word?What are big-endian and little-endian assignments of addresses? ?(Nov,07)

27. Write notes on Instruction formats? ?(Nov,07)

28. List the various addressing modes.Give a brief explanation of each of them with eg? (Nov,07)

29. Describe the organization of stack?(Nov,07)

30. Briefly explain any six I?O operations with an eg? (May 07)

31. Illustrate memory read and write operations? (May 07)

32. Design a multiplier that multiplies two 4-bit numbers. (May 07)

33. Describe the algorithm for integer division with suitable examples. (May 07)

UNIT II

2 Marks

1. Compare hardwired and micro programmed controls. (Nov/Dec2013)

2. What is nano programming? (Nov/Dec2013)

3. Write the register transfer sequence to read a word from memory. May/June(2013)

4. What is a micro program sequencer? May/June(2013)

5. Write the register transfer sequence for storing a word in memory. May/June(2012)

6. What is hard-wired control? How is it different from micro-programmed control? May/June(2012)

7. Write the difference between Horizontal and Vertical Microinstructions. May(2011)

8. In what ways the width and height of the control memory can be reduced? May(2011)

9. What is mono phase? (Nov/Dec2010)

10. What are the two possible error conditions that may arise in a stack operation? (Nov/Dec2010)

11. Under what situations the micro program counter is not incremented after a new instruction is fetched from micro program memory?(may ’10)

12. what are the relative merits of horizontal and vertical microinstructions format? (may ’10)

13. State the differences btw hardwired and microprammed control unit? (May 07),(Nov ’07)

UNIT II

16 Marks

1. Explain the following: Address sequencing in control memory.(8)

Micro program sequencer (8) (Nov/Dec2013)

2. Explain Multiple bus organization.(8) (Nov/Dec2013)

3. Explain the design of hardwired control unit.(8) (Nov/Dec2013)

4. Explain the design of micro-programmed control unit in detail.(16) May/June(2013)

5. Explain the execution of a three operand instruction using multiple bus organization.(8) May/June(2013)

6. Write notes on nano programming.(8) May/June(2013)

7. With a neat diagram explain the internal organization of a processor. May/June(2012)

8. Explain how control signals are generated using micro-programmed control. May/June(2012)

9. Explain the use of multiple-bus organization for executing a three operand instruction. May/June(2012)

10. Explain the design of hardwired control unit. May/June(2012)

11. Describe the control unit organization with a separate Encoder and Decoder functions in a hardwired control. (8) )May(2011)

12. Generate the logic circuit for the following functions and explain. (8)

Z in = T1 + T6 .ADD + T4 .BR + ..... )May(2011)

13. Draw the diagram of the single Bus organization of the data path inside a processor?

14. Explain the above regarding execution. ?(Nov 2010)

15. Explain the organization of the control unit to allow conditional branching in the microprogram.

16. How is a functional field microinstruction generated?Explain?(Nov 2010)

17. Draw and explain the block diagram of a complete processor? ?(may ’10)

18. Briefly describe the design of ahardwired control unit?(may ’10)

19. Explain the basic organization of a microprogrammed control unit and the generation of control signals using microprogram? ?(may ’10)

20. What are advantage and disadvantages of hardwired and microprogrammed control?(may ’10)

21. Explain instruction cycle highlighting the sub-cycles and sequence of steps to be followed? (Nov,07)

22. Draw the single bus and three bus organization of data path inside a processor? (Nov,07)

23. Describe the organization of microprogrammed control? (Nov,07)

24. Give the block diagram of the hardwire implementation of addition and subtraction of signed number and explain the operations with flowchart? (May 07)

25. Explain the representation of floating point numbers in detail. (May 07)

26. Explain the execution of instruction with diagram? (May 07)

27. Explain multiple bus organization? (May 07)

UNIT III

2 Marks

1. What is meant by data hazards in pipelining? (Nov/Dec2013)

2. Define pipeline speed up. (Nov/Dec2013)

3. What is meant by hazard in pipelining? Define data and control hazards. May/June(2013)

4. Why is branch prediction algorithm needed? Differentiate between the static and dynamic techniques. May/June(2013)

5. What is meant by data and control hazards in pipelining? May/June(2012)

6. What is meant by speculative execution? May/June(2012)

7. What hazard does the above two instructions create when executed concurrently? May/June(2011)

8. What are the disadvantages of increasing the number of stages in pipelined processing? May/June(2011)

9. How can memory access be made faster in a pipelined operation? Which

hazards can be reduced by faster memory access? (Nov/Dec2010)

10. How do you calculate the execution time T of a program that has a dynamic

instruction count N? (Nov/Dec2010)

11. What is pipelining and advantages. ?(may ’10)

12. List the key aspects in gaining the predominance in pipelined systems? ?(may ’10)

13. What is datapath? (may ’10)

14. What are the design methods for control units? (may ’10)

15. What is a pipeline control? (may ’10)

16. What is data hazard in pipelining?What are the solutions? (Nov,07)

17. Define pipeline speedup? (May 07)

UNIT III

16 Marks

1. Describe the data and control path techniques in pipelining.(10) (Nov/Dec2013)

2. Briefly explain the speedup performance models for pipelining.(6) (Nov/Dec2013)

3. What is instruction hazard?Explain in detail how to handle the instruction hazards in pipelining with relevant examples.(10) (Nov/Dec2013)

4. Write note on exception handling.(6) (Nov/Dec2013)

5. Explain a 4-stage instruction pipeline. Also explain the issues affecting pipeline performance.(10) May/June(2013)

6. Explain dynamic branch prediction technique.(6) May/June(2013)

7. Explain the relation between pipelined execution and instruction feature.(6) May/June(2013)

8. Describe the techniques for handling control hazards in pipelining.(10) May/June(2013)

9. Discuss the basic concepts of pipelining. May/June(2012)

10. Describe the data path and control considerations for pipelining. May/June(2012)

11. Describe the techniques for handling data and instruction hazards in pipelining. May/June(2012)

12. What are the hazards of conditional branches in pipelines? how it can be resolved? (16) May(2011)

13. Explain super scalar with neat diagram(16) May(2011)

14. Explain how the instruction pipeline works.What are the various situations where an instruction pipeline can stall?What can be its resolution? ?(Nov 2010)

15. Examine the relationships between pipeline execution and addressing modes?

16. What do you mean by out of order execution? ?(Nov 2010)

17. Describe the role of cache memory in pipelining system?(may ’10)

18. Discuss the influence of pipelining on instruction set design.?(may ’10)

19. What is instruction hazard? Explain the methods for dealing with the instruction hazards? (may ’10)

20. What is data hazard?Explain the methods for dealing with the data hazards. May(2008)

21. What is branch hazard?Describe the methods for dealing with the branch hazards?

22. May(2008)

23. Explain the different types of hazards that can occur in a pipeline? (Nov,07)

24. What are superscalar processors? Explain the typical structure superscalar processor? (Nov,07)

25. Design a 4-stage instruction pipeline and show how its performance is improved over sequential execution? (Nov,07)

26. Explain the function of a six segment pipeline and draw a space diagram for asix segment pipeline showing the time it takes to process eight tasks. (May 07)

27. Explain how the performance of the instruction pipeline can be improved? (May 07)

UNIT IV

2 Marks

1. Compare static RAM and Dynamic RAM. (Nov/Dec2013)

2. Define the terms hit,miss and ratio with respect to cache. (Nov/Dec2013)

3. An address space is specified by 24 bits and the corresponding memory space by 16 bits:

How many words are there in the virtual memory and in the main memory? May/June(2013)

4. What is meant by an interleaved memory? May/June(2013)

5. What is meant by an interleaved memory? May/June(2012)

6. An address space is specified by 24 bits and the corresponding memory space by 16 bits:

7. How many words are there in the May/June(2012)

a) Virtual memory

b) Main memory

8. What is the use of EEPROM? May(2011)

9. State the hardware needed to implement the LRU in replacement algorithm. May(2011)

10. What is memory interleaving? (Nov/Dec2010)

11. How is disk access time calculated? (Nov/Dec2010)

12. Define Random Access memory? ?(Nov 2010)

13. What are the advantages of using Virtual memory?(Nov 2010)

14. How many memory chips are needed to construct 2M x 16 memory system using 512 K x static memory chips?(may ’10)

15. What is virtual memory and what are the benefits of virtual memory? ?(may ’10)

16. What will be the width of the address and data buses for a 512 k x 8 memory chip? (Nov,07)

17. list the diff. between Static RAM and Dynamic RAM. May(2008)

18. Define the terms :Spatial locality and temporal locality. May (2008)

19. What is virtual memory?How it is implemented? (Nov,07)

20. List the factors that determine the storage device performance? (May 07)

21. How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes? (May 07)

UNIT IV

16 MARKS

1. Explain the need for memory hierarchy technology, with a four level memory.(6) (Nov/Dec2013)

2. Explain the various mapping techniques associated with cache memories.(10) (Nov/Dec2013)

3. Explain a method of translating virtual address to physical address.(6) (Nov/Dec2013)

4. What for replacement algorithms are used? Explain the important ones.(10) (Nov/Dec2013)

5. Draw the block diagrams of two types of DRAMs and explain.(10) May/June(2013)

6. Explain address translation method in virtual memory.(6) May/June(2013)

7. Explain the various mapping techniques associated with cache memories.(10) May/June(2013)

8. Write short note on magnetic hard disks.(6) May/June(2013)

9. In a cache-based memory system using FIFO for cache page replacement, it is found that the cache hit ratio H is low. The following proposals are made for increasing. May/June(2012)

a) Increase the cache page size

b) Increase the cache storage capacity

c) Increase the main memory capacity

d) Replace the FIFO replacement policy by LRU.

Analyze each proposal to determine its probable impact on H.

10. Explain the various mapping techniques associated with cache memories. May/June(2012)

11. Explain a method of translating virtual address to physical address. May/June(2012)

12. What is a mapping function? what are the ways the cache can be mapped? May(2011)

13. Explain the organization and accessing of data on a disk? May(2011)

14. Explain synchronous DRAM technology in detail. May(2011)

15. Write a note on Asynchronous and Synchronous DRAM’s. ?(Nov 2010)

16. Analyze the memory hierarchy in terms of speed,size and cost? ?(Nov 2010)

17. Explain the Address translation in Virtual Memory? ?(Nov 2010)

18. Draw the neat sketch of memory hierarchy and explain the need of cache memory?(Nov 2010)

19. Explain the organization of magnetic disk in detail. ?(Nov 2010)

20. What are the different secondary storage devices? Elaborate on any one of the device? (may ’10)

21. Explain how the virtual address is converted into real address in a paged virtual memory system? (may ’10)

22. Explain approaches for addressing multiple-module memory systems with suitable diagrams? (may ’10)

23. Briefly describe magnetic disk principles and also the organization and accessing of data on a disk? ?(may ’10)

24. Describe the functional characteristics that are common to the devices used to build main and secondary computer memories. May(2008)

25. Explain various mechanisms of mapping main memory address into cache memory addresses. May(2008)

26. Explain how the virtual address is converted into real address in a paged virtual memory system. May(2008)

27. Describe the working principle of a typical magnetic disk. May(2008)

28. Write short notes on static memories? (Nov,07)

29. Explain the concept of memory hierarchy? (Nov,07)

30. Write notes on (Nov,07)

1.ROM techologies

2.Memory interleaving

3.Set associative mapping of cache.

4.RAID disk arrays.

31. What is virtual memory? Explain how the logical address is translated into physical address in the virtual memory system with a neat diagram? (May 07)

32. Describe the organization of a typical RAM chip. (May 07)

33. Explain the organization of magnetic disk in detail. (May 07)

34. A digital computer has a memory unit of 64K x 16 and a cache memory of 1K words.the cache uses direct mapping with ablock size of four words.how many bits are there in the tag,index,block and word filelds of address format?How many blocks can bthe cache accommodate? (May 07)

UNIT V

2 MARKS

1. What is DMA?Mention its advantages. (Nov/Dec2013)

2. What is meant by vectored interrupt? (Nov/Dec2013)

3. Distinguish between isolated and memory mapped I/O? May/June(2013)

4. Mention the advantage of USB. May/June(2013)

5. Specify the different I/O transfer mechanisms available. May/June(2012)

6. What does isochronous data stream means? May/June(2012)

7. What is distributed arbitration? May(2011)

8. How interrupt requests from multiple devices can be handled? May(2011)

9. Define an interrupt. ?(Nov 2010)

10. What are Priority groups? (Nov 2010)

11. What are the operating system routines of a keyboard driver? (Nov 2010)

12. What are the possible data transfer modes available with peripherals. ?(Nov 2010)

13. What is meant by bus arbitration? ?(may ’10)

14. Name and give the purpose of widely used bus standard? ?(may ’10)

15. What factors influences the bus design decisions? May(2008)

16. What is priority interrupt? May(2008)

17. Why does DMA have priority over the CPU when both request a memory transfer? (May 07)

18. What is the Advantage of usiung interrupt initiated data transfer over transfer under program control without interrupt? (May 07)

19. Why we need DMA? Nov,07)

20. What is the difference between subroutine and interrupt service routine? Nov,07)

UNIT V

16 MARKS

1. Design a parallel priority interrupt hardware for a system with eight interrupt sources and explain.(8) (Nov/Dec2013)

2. Explain USB interface.(8) (Nov/Dec2013)

3. Write a short note on I/O processor.(6) (Nov/Dec2013)

4. What is the need for an I/O interface?Describe the functions of SCSI interface with a neat diagram.(10) (Nov/Dec2013)

5. Explain the following:

(a)Interrupts (10) May/June(2013)

(b)Buses (6) May/June(2013)

6. Explain interface circuits.(8) May/June(2013)

7. Discuss about PCI buses.(8) May/June(2013)

8. Explain the following: May/June (2012)

i. Interrupt priority schemes

ii. DMA

9. Write an elaborated note on PCI, SCSI and USB bus standards. May/June(2012)

10. How data transfers can be controlled using handshaking technique? (8)

11. Explain the protocols of USB. (8) May(2011)

12. How the parallel port output interface circuit works? (16) May(2011)

13. Explain the following (Nov 2010)

a) Memory mapped I/O

b) I/O Registers

c) Hardware Interrupts

d) Vectored interrupt

14. Write a notes on SCSI bus. Explain with a neat diagram ?(Nov 2010)

15. Explain the difference between CISC and RISC processors? ?(Nov 2010)

16. Explain the DMA mode of Data transfer. ?(Nov 2010)

17. Describe the hardware mechanism for handling multiple interrupt requests. ?(may ’10)

18. What are handshaking signals?Explain the handshake control of data transfer during input and output operation. ?(may ’10)

19. What are the needs for I/O interface?Explain the function of a typical 8-bit parallel interface in detail. ?(may ’10)

20. Describe the USB architecture with the help of a neat diagram. ?(may ’10)

21. Draw the typical block diagram of a DMA controller and explain how it is used for direct data transfer between memory and peripherals. May(2008)

22. Describe the working principles of USB May(2008)

23. Briefly compare the characteristics of SCSI with PCI May(2008)

24. Design a parallel priority interrupt hardware for a system with eight interrupt sources? (May 07)

25. Describe the functions of SCSI with a neat diagram. (May 07)

26. What is the importance of an I/O interface?Compare features of SCSI and PCI interfaces. (May 07)

27. What are the different iput and output signals of DMA controller?Why are the Read and Write control signals are bidirectional?Under what condition and for what purpose they are used as inputs and outputs? (May 07)

28. Explain how I/O devices can be interfaced with a block diagram (Nov,07)

29. How do you connect multiple I/O devices to a processor using interrupts?Explain with suitable diagrams. Nov,07)

30. Write notes on DMA,Bus Arbitration,Printer-Processor Communication,USB. (Nov,07)

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