University of Southern California



EE457 -- Virtual Memory Acronyms and Concepts needed for the Midterm ExamAcronyms:MMU = Memory Management UnitVA = Virtual AddressPA = Physical AddressVPN = Virtual Page NumberPPFN = Physical Page Frame NumberTLB = Translation Look-aside BufferPT = Page TablePTBR = Page Table Base register Concepts:1. Divide VA into VPN and Page Offset (PO), similarly divide PA into PPFN and Page Offset (PO), based on the Page size (page size = virtual page size = physical page size).If page is set to 4KB = 212, then the VA is divided as VPN = VA[31:12] and PO = VA[11:0]. Then PPFN = PA[31:12] and PO = PA[11:0].2. Fully Associative mapping is necessary between Virtual Pages and Physical Page Frames.However parallel search by 220 comparison units each of 21 bits (1-bit valid/presence + 20-bit stored VPN) in a CAM is prohibitively expensive. So, we decided to have a Full-length table (having one entry for each VPN of the 220 VPNs) so that it can be indexed with the VPN. The entry contains PPFN (20 bits), a presence bit (1 = present, 0 = absent), and a few other bits. The few other bits generally include three protection bits (to indicate whether the page is readable, writable, executable), a dirty bit (to indicate whether the page got modified during its stay in MM and requires to be written back to the disc eventually) and LRU bits to implement a pseudo LRU to arrive at a victim to be replaced. 3. Page Table is a look-up table. Each process has a PT of its own. Several page tables are in the main memory simultaneously (as shown in the yellow area of the diagram below). So, it is important that we do not consume too much memory in MM to hold a page table. So, we went for a Multi-Level page table. PTBR in the MMU holds the starting address of the page table for the currently running process. PTBR is loaded with the starting address of the page table (starting address of the top-level page table) of the process, that is being switched in during context switching by the OS (Operating System).2533650718185(computing)#/media/File:Process_states.svg When time permits, please read the initial part of the Wikipedia page on Process (computing): (computing) 020000(computing)#/media/File:Process_states.svg When time permits, please read the initial part of the Wikipedia page on Process (computing): (computing) 4. The Multi-Level page table caused a disadvantage. Now VPN to PPFN (VA to PA) translation time is increased because you need to access multiple levels of the PT. For example, in a 3-level page table system, you need to access the A-level Table (also called the Page Directory or the 1st level table) followed by the B-level table (2nd level page table or simply page table in the 2-level page table system of old Intel processors) followed by the C-level table (3rd level page table). All three access are to the main memory. To solve the latency problem, we added TLB to MMU. TLB is a cache to the PT.5. Two types of TLBs. 5.1 Earlier processors have a small TLB (say 64-entry Fully Associative TLB). It is flushed on context switch. It will incur several TLB misses initially (immediately after context switch) (these are called cold misses) but very soon it stabilizes and will have a very high hit rate. 5.2 Current Multi-Threaded processors have a big TLB and it includes PCID (Process Context ID) besides the TAG, so that it can hold translations for several processes simultaneously. It does not need to be flushed on context switch. Some people call it ASN (Address Space Number) instead of PCID.6. Address coming out of the inner CPU (the red rectangle in the figure below) is Virtual Address (VA). Address coming out of CPU Chip (the blue rectangle) is Physical Address (PA). Please see the figure below, which is a copy of page 59/61 of the notes pdf file below: . Dirty bits are held at three paces. See the last two pages of the above class notes pdf .8. TLB entries are “singular”. The concept of a multi-word block (like a 4-word block in the cache) doesn’t exist (cannot exist) in the context of the TLB, because, there is no guarantee that if the PT has translation for one VPN, it should also have a translation for the adjacent VPN. 9. In the 32-bit address systems, Intel thoughtfully divided the 20-bit VPN into two 10-bit fields so that the Page directory and the 2nd level page tables are all 1K x 32-bit words (or 4KB). So, each of these occupies a 4KB page frame. ................
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