CSD Syllabus



CSDAn introduction to digital systems using VHDL and to microcontroller applications using CTable of content This table of content is accompanied by references to each topic. Mainly, the references are examples, exercises, projects and class notes from digsys.upc.edu, but you can find slides and book chapters from all over the Internet. Be aware that for materials, which are not ours, the symbols, naming conventions and writing styles are different and thus, they must be renamed and reorganised in order to be in use in our CSD subject as valuable study materials. Combinational circuitsIntroduction to digital electronicsLogic gates Circuits and logic diagrams Buffer (non-inverter)Inverter (NOT)AND, NANDOR, NORXOR, NXORTri-state Equations in Boole’s AlgebraTruth table and canonical equationsSum of minterms Product of maxtermsTiming diagramsBoolean functionsPropertiesDuality principleProduct of sums (PoS)Sum of products (SoP)Any type of equation or non-standard formsWolfram Alpha engine for calculating truth tables and deducing logic circuitsMinimization of logic functions and circuitsKarnaugh Maps (not covered)Espresso heuristic algorithm: minilog.exe, Logic Friday (not covered)Minilog text formatMinilog minimisation table formatDon’t-cares inputs (‘x’ or ‘-‘)Incomplete functions: don’t-cares outputsHardware description languagesVHDLVerilog (not covered) Commercial standard chips for logic gatesLogic familiesTTL, LS-TTL, HC, HCT, etc. (not covered)CMOSStandard chip references Electrical characteristics of logic gatesVoltage levelsPower dissipationPropagation delay and maximum speed of operationVirtual laboratory and simulation of electronic circuitsSPICE algorithmsProteus ISIS from Labcenter Electronics Multisim from National Instruments (not covered)Digital simulatorsHades: interactive simulation framework (not covered)Deeds: Digital electronics education and design suite (not covered)Printed circuit board (PCB) designEagle (not covered)Fritzing (not covered)Designing combinational circuits using VHDLDesign flow using EDA toolsSpecifyPlanDevelop (circuit synthesis)Verification using a VHDL test benchFunctional simulationGate-level simulationPlan A: single-file structural (equations)Canonical equations: sum of minterms, or product of maxtermsMinimised equations: SoP or PoS (from minilog.exe)Only-NOR gatesOnly-NAND gatesAny kind of nonstandard equation Plan B: single-file behavioural / high level /algorithm description Translating the truth tableThe truth table as a flowchartPlan C1: Single-file hierarchical design (not recommended)Plan C2: Hierarchical design (components and signals)The method of decoders (MoD) The method of multiplexers (MoM)The method of ROM memory cells or RAM lookup tables (covered in Chapter 2)Any combination of methods and equationsStandard combinational logic circuits Design flow and EDA toolsSpecifications Symbol or entity, truth table, timing diagram, equations or algorithmHow to design larger multiplexers using smaller components of the same kind (plan C2)?Commercial standard references Plan A, B, C2Development using EDA synthesis toolsSimulation using VHDL testbenchGate-level simulation, propagation delay and maximum speed of computing Laboratory prototyping using CPLD/FPGA training boards Multiplexer: MUX_2, MUX_4, MUX_8, etc.Demultiplexer: DeMUX_2, DeMUX_4, etc.Encoders (priority high): Enc_3_8, Enc_4_16, etc. Binary decoder: Dec_2_4, Dec_3_8, etc. Hexadecimal to 7-segment decoder: HEX_7seg_decoderCommercial standard logic chips in classic technologiesBinary codes and code convertersRadix-2 and radix-16 number systemsGrayBCDOne-hot and one-coldJohnsonASCII, etc. Binary numbers and arithmetic circuitsAddition 1-bit adder (Adder_1bit)n-bit adder (Adder_4bit, etc.) Ripple-carry adderCarry-lookahead adderOnes counterMultiplier (Mult_8bit)Comparator 1-bit comparator (Comp_1bit)n-bit comparator (Comp_4bit, etc.)Two’s complement binary numbers (signed integers)SubtractorAdder-Subtractor (Int_Add_Subt_8bit, etc.)Arithmetic Logic UnitMultiplier (Int_Mult_8bit)Comparator (Int_Comp_8_bit, etc.)Parity generators and checkersCommercial standard arithmetic chips in classic technologiesProgrammable logic devices (PLD) and EDA tools for VHDL projectsUsing a programmable array (PAL) to implement a logic functionClassic sPLD ispGAL22V10Complex Programmable Logic Device (CPLD)Field Programmable Gate Array (FPGA)EDA tools for circuit synthesis ispLEVER Classic / DiamondXilins Vivado / ISE Intel Quartus Prime / Quartus II VHDL simulation toolsVHDL testbench schematic for combinational circuitsALDEC Active HDL Lattice EditionXilinx ISimMentor Graphics ModelSim Intel FPGA Starter Edition Other examples and applicationsQuestionnairesProblemsPreliminary laboratory assignments (PLA)Sequential systems The concept of memory in digital circuits. Current state and next stateLatch RS. Asynchronous 1-bit memory cell Function table, state diagram, timing diagramHow to design a latch RS using gatesAn RS latch circuit (RS_latch) using plan ARS latch as a push-button debouncing circuitFlip-flop. Synchronous 1-bit memory cellThe concept of a CLK signal. SynchronicityCLK circuitsRC Quartz crystalIntegrated circuit 555The concept of clear direct (CD) or asynchronous resetPower-ON reset and initialisationTypical flip-flopsDeducing the circuit of an RS flip-flop from the RS latch, CLK’s rising-edge detectorD, JK, and T flip-flops: symbol, state diagram, timing diagram Analysis of asynchronous and synchronous circuits based on flip-flops and logicMassive digital memories Symbol, address and dataGeneral architectureROM (read only memory)VHDL circuit (ROM_2^nxm)Method of ROM for implementing logic functions in VHDL, look-up tables (LUT)RAM (random access memory)VHDL circuit (RAM_2^nxm) and the idea of intellectual property (IP) specific circuits for a given target technologyTri-state buffer in VHDLArchitecture of a Finite State Machine (FSM)State register: r-bit memory (D_FF), state encoding (binary sequential, one-hot, etc.)Next state logic (CC1), truth table, behavioural interpretation: flowchart Output logic (CC2), truth table, behavioural interpretation: flowchartPropagation delay from CLK to output (tCO), maximum frequency of operation of a FSMFSM in VHDL: a single-file projectVHDL testbench schematic for sequential systems: CLK and stimulus processesDesigning flip-flops as FSMRS flip-flop (RS_FF)D-type (data) flip-flop (D_FF)JK flip-flop (JK_FF)T-type (toggle) flip-flop (T_FF) Examples of applications based on FSMClassroom luminaries controlPush-button debouncing filterMatrix keypad encoderTraffic light controllerStepper motor controllerStandard sequential systems as FSMBinary counters Symbol, function table, modulo, timing diagram, state diagramControl signals: count enable (CE), up and down (UD_L) or reversibility, parallel load (LD) or output value presetOutputs: binary code (binary sequential, BCD, one-hot, Gray, Johnson, etc.), terminal count (TC) pulsePlan X: designing counters as FSM, single-file VHDL project (Counter_mod12, Counter_BCD_1digit)Plan Y: designing counters using the VHDL arithmetic library and STD_LOGIC_VECTOR, single-file VHDL project (Counter_mod16)Count truncation, expanding counters (Hour_counter)Plan C2: designing counters using a hierarchical structure, standard components and logic, VHDL multiple-file projectData register (Data_reg_nbits). Parallel loadShift register (Shift_Data_reg_nbits. Shift left, shift right, parallel loadCommercial standard sequential chips in classic technologiesDedicated processorsArchitecture of an advanced digital systemDatapath (operational) unit, data input/output, status signals and flagsControl unit (FSM). Control signals, external inputs and outputsCLK generator Frequency divider Pulsed to square waveform converter using T_FF Adaptable generic structureExamples and applications of dedicated processorsSerial multiplierSerial adderSerial asynchronous receiver and transmitter subsystem (SART)Pulse generatorMM:SS timerOther examples and applicationsQuestionnairesProblemsPreliminary laboratory assignments (PLA)MicrocontrollersArchitecture and basicsMicroprocessorMicrocontroller Harvard – Von Neumann architecturesPIC18F4520 architectureAssembler and CMPLABX: Microchip Integrated Development environment (IDE) and XC8 C compilerDigital inputs and outputs: example of a combinational circuit in C:Hardware schematicPolling switches and digital levelsCLK and reset circuitsDriving LED Software programI/O port configuration register (TRIS)Program organisation: setup (init_system) and main loop (read_inputs, truth_table, write_outputs)Development & testingProject compilation and chip configuration files hex, cofProteus simulation and testing. Step by step debugging, watch variables windowPrototyping Solving FSM in CInterrupts. External event detection. Push-buttonsoutput_logicstate_logicPeripherals: LCDPeripherals: timer0,Other examples and applicationsQuestionnairesProblemsPreliminary laboratory assignments (PLA) ................
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