Eee.guc.edu.eg
Faculty of Information Engineering & Technology Dr. M. Abd El Ghany
Electrical & Electronics Department Eng. Heba Elhosary
Course: Microelectronics Lab ELCT605
Spring 2021
Digital Lab Report 2
Introduction to Vivado
and
Xilinx FPGAs design flow
|Name |ID |Lab Group |
| | | |
| | | |
▪ Lab Task: 3x8 Decoder
1. Tabulate the truth table of 3x8 decoder.
2. Draw the logic diagram of 3x8 decoder.
3. Create a VHDL module named “ Decoder_3x8” .
4. Write a test bench to Test your VHDL code for the following cases “ 000” , “010”, “110”, and “111”.
5. Tabulate the truth table of the full adder
6. What is the size of decoder needed to implement a full adder using a decoder? Explain.
7. Show how the full adder can be implemented using the chosen Decoder size. Draw the logic diagram.
8. Update your VHDL do the function of the circuit discussed above.
9. Write a test bench to Test your VHDL code for the following cases “ 000” , “010”, “110”, and “111”.
▪ Lab Task: common Anode BCD-to-7 segment Decoder
1. Tabulate the truth table of the BCD-to-7 segment decoder.
2. Derive the output equations of the BCD-to-7 segment decoder.
3. Draw the logic diagram of the BCD-to-7 segment decoder.
4. Create a VHDL module named “BCD_Decoder”.
5. Write a testbench to test your VHDL code. Use the following test cases:
Input = 0011, 0101 and 1001. Include a screen shot of your adjusted input test cases.
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Grade: /30
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