Assignment Overview
VHDL Assignment 4 Assignment Overview In this assignment you will use Vivado Webpack to write and simulate a display MUX and decoder that will activate one 7-segment display at a time on the VCD Simulator and put the appropriate data on each particular display. It is recommended that you read through this entire document at least once before beginning on the project to get an understanding of what you will be doing (don’t blindly follow steps, you want to understand what you’re doing and why). If you are confused or have any questions first look back at the previous assignments for context and examples, and watch the prime detector video with sound so you can hear the debugging and downloading steps. If this doesn’t help, then contact your instructor(s) and TA(s). Engineering is about paying attention to details so when working on the steps below, be sure to read each word of the step and check off each step sequentially. Background As shown in Assignment 2, the 7-segment displays on the Basys 3 boards have all the same data input lines. Each 7-segment is turned on or off using the an(3 downto 0) outputs. In order to make use of these displays for our ALU (lab 3) we need to design something that will put the proper data on the proper 7-segment digit in the display. We are going to have 4 switches as the inputs to each 7-segment display, as well as two special cases for displaying a blank or a negative sign on a particular digit. Figure 1 shows which 4 switches will correspond to which 7-segment digit.Figure 1. The switches and corresponding 7-segment outputs.In order to send the appropriate data to the appropriate display, we must cycle through turning on each individual display, and at the same time place the corresponding data on the 7-segment outputs. This should cycle through repeatedly and should happen fast enough to not be noticed by anyone looking at the display. That is, even though only one display will ever be on at a time, the cycling through each display should be fast enough to trick the human eye into seeing all 4 on at a time. This is called Persistence of Vision and is used in most displays. For instance, you can’t tell that your computer monitor is refreshing the screen 60 times per second, everything looks smooth and fluid when your mouse moves on screen. Similarly, when you watch an older CRT tube tv, you don’t notice that only half of the screen is being updated at a time (those displays typically draw the 525 lines from top to bottom of the screen about 60 times a second, but they only draw the odd lines first, then come back and draw the even lines). The way we will accomplish the task of displaying data on only one 7 segment at a time will be to cycle through a simple finite state machine. Finite state machines have a number of “states” in which certain outputs are generated. (This particular type is called a Moore state machine). After a certain input, the machine moves from one state to another, thereby changing the outputs to those of the new state. In our case we will have 4 states, one for each 7-segment digit in our display.A finite state machine of this type is easily implemented as a CASE structure in VHDL. Each case detecting a particular state value, and setting up what the next state should be. DatatypesIn the last project, we learned of unsigned datatypes and we already knew about STD_LOGIC and STD_LOGIC_VECTOR datatypes. In this project, we will create our own type. This is simple to do in VHDL, all we must do is declare the name for the new datatype, then declare all the possible values it can be. In this case, we will create a new datatype called ”state” and we will declare the only valid values for this new type to be State_0, State_1, State_2, and State_3. This is done in the architecture of our code in the same place we would normally declare signals.Clock DividerSince finite state machines (FSMs) are sequential circuits, we will be using a clock signal on our hardware. The clock on the Basys 3 is much too fast, so we’ll need to divide the clock signal before using it to step through our states. Getting started Create a directory to store all of the assignment’s files. Open Vivado and create a new project called computer_assignment_4. It will be an RTL projectNo sources to input. Although if the target and simulation languages aren’t set to vhdl, change them to vhdl. Figure 2. The languages should both be set to VHDL.No existing IP. No constraints file. The Basis3 uses an XC7A35T-1CPG236C FPGA ○ CPG236 packaging ○ Speed grade -1 Figure 3. Select the chip on the Basys3 board.Task This task is to implement a state machine that works as a mux to select from 4 different sets of inputs data, and a decoder to turn on only one of the 7 segment digits at a time Add a new source names sevenSegMux. The inputs and outputs should match the entity shown in Figure 4.-31289643413443Figure 4. The sevenSegMux layout showing the sevenSegDecoder component and two processes, one clock divider which changes state and is connected to the second process which contains the state machine. The inputs of these processes are to be listed in the sensitivity list. The outputs are signals which are port mapped to the component.00Figure 4. The sevenSegMux layout showing the sevenSegDecoder component and two processes, one clock divider which changes state and is connected to the second process which contains the state machine. The inputs of these processes are to be listed in the sensitivity list. The outputs are signals which are port mapped to the component.The behavior of the overall of the sevenSegMux is controlled by the state machine in Figure 5.Figure 5. The state machine for the sevenSegMux does all the heavy lifting of displaying the appropriate data on the appropriate digit of the display on the Basys 3 board. While states 0,1 and 3 are basically the same except the next_state and display data, State_2 performs a few interesting tasks before deciding what to display, deciding whether or not it should be blank, display the number on in2, or show a negative sign.To get started, Add a new source, and select the source file sevenSegDisplay from your Lab 2 assignment found in project2\project2.srcs\sources_1\new\sevenSegDisplay.vhdCreate a new source file named sevenSegMux with the inputs and outputs shown in Figure 4. Use the code below which contains the clock divider process and a start to your state machine process.library IEEE;use IEEE.STD_LOGIC_1164.all;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned valuesuse IEEE.NUMERIC_STD.all;-- Uncomment the following library declaration if instantiating-- any Xilinx leaf cells in this code.--library UNISIM;--use UNISIM.VComponents.all;entity sevenSegMux isport ( --add your code here Based on Figure 4.0);end sevenSegMux;architecture Behavioral of sevenSegMux is-- ADD YOUR sevenSegDecoder COMPONENT HERE --Make a simple FSM which will act as a mux, a 2:4 decoder and decodes when the negative should be display type State is (State_0, State_1, State_2, State_3); --make our own custom datatypesignal current_state, next_state : State;signal shouldShowNegative : std_logic;signal data : STD_LOGIC_VECTOR(3 downto 0); -- buffer to hold the 7-segment input dataconstant counter_max : unsigned(15 downto 0) := x"8000"; --fpgasignal counter_sel : unsigned(1 downto 0) := "00";signal counter : unsigned(15 downto 0) := x"0000";begin -- begin architecture-- ADD YOUR sevenSegDecoder PORT MAP HERE--simple clock_divider and changes the stateclock_divider : process (clk)beginif (clk'EVENT and clk = '1') thencurrent_state <= next_state; --state gets updated here.end if;end process clock_divider; --state machine process. Each state sets up the “an” outputs, what input connects to the “data“ output, sets the value of the “next_state”, and decides whether the 3rd digit from the left should show a negative or be blank. Each state here corresponds to 1 digit on the 7-segment displaystate_machine : process (current_state, in0, in1, in2, in3, neg, blank)begincase current_state is when State_0 => shouldShowNegative <= '0'; --Don’t show a negative sign on this digitan <= "1000";data <= in0;next_state <= State_1; when State_1 => --Add your code here when State_2 => --Add your code here--Turn off this digit if blank = 1--If blank = 0, then decide to set data to in2 as normal, or make shouldShowNegative = 1 when State_3 => --Add your code here end case;end process state_machine;end Behavioral;Continue to create the rest of the file. Here are some helpful hints: Don’t stray from the template of the code provided above too much as far as the structure of it goes.States 0, 1, and 3 are very similar, but State_2 has some decisions to make. If the blank input =1, then turn off the digit so nothing displays. You can do that by turning off the an pin associated with that output. Eg. an <= "1111";If blank input = 0, then you will either display the data on in2 or you will display a negative signBuild a TestbenchThere’s no easy way to testbench this particular assignment to full fidelity. There are over 1,000,000 possible combinations of inputs. We could simulate all of them, but it would take a long time to verify all combinations. Instead of doing all of the possible combinations, we will simply simulate each display while the other 3 displays are showing “0”. This brings our possible combinations of inputs down to about 650. Create a new testbench file named “displayMux_tb”Add no inputs or outputs.Paste in the code in the Appendix. This code is important to understand for when you have to write your own testbenches. It does the following:Creates signals we will use to control the inputs and map outputs during the simulation. We need a clk (clock), sw(15 downto 0) which are the switches, btns(4 downto 0) which are mapped to the buttons whose corresponding bits represent btnC, btnL, btnD, btnR, btnU respectively. The individual 7-segment data lines controlling the LEDs are seg(0 to 6), and the anodes to control which display is being activated at a time an(3 downto 0). Bring in a component of your sevenSegMux and instantiate it and portmap the inputs of the top (the switches, 7 segments, an, btnU, btnC, and clk) to the components inputs and outputs. Refer to Figure 6 to see how to map the appropriate switches and 7-segs, etc. to the appropriate inputs using signals. Figure 6. An X-ray of the displayMux_tb top schematic showing the sevenSegMux component and how to name your signals such that the outputs work on the board.Open the simulation settings by right-clicking “Run Simulation” and selecting “Simulation Settings” Select the “simulation” tab and change the “simulation time” to 650nsMake sure it’s syntax error free and can be simulated. Take a screenshot of this waveform chart for your report.Create the VCD file and use the graphical simulatorThe first step we will need to take is to change the simulation time in vivado and rerun the simulation. Open the simulation settings by right-clicking “Run Simulation” and selecting “Simulation Settings” Select the “simulation” tab and change the “simulation time” to 1nsRerun the simulationWith the simulation opened, run the following commands in the TCL console:open_vcdlog_vcd [get_objects /displayMux_tb/*]run 650nsclose_vcdOpen the VCDSimulator and import the dump.vcd file. It will be in the project folder’s simulation path. For instance if my project was named “project_4” and was saved on my desktop the path to the dump.vcd file would be:C:\Users\ALaptop\Desktop\project_4\project_4.sim\sim_1\behav\xsim\dump.vcdAssign the signals to the appropriate inputs and outputs in the simulator.Set sw to switches and select every switch for use.Set “an” to the anodeSet “seg” to the 7-segmentAnd set “btns” to the buttonsClick “Done”To test, you will select a group of 4 switches at a time. The upper 4 switches(15 to 12) control the leftmost display, the next 4 (11 to 8) the middle-left display, switches 7 to 4 control the middle-right display and the 3 to 0 switches control the rightmost display. When testing one display all others must be set to 0. Since we didn’t define any other states for these switches in the testbench (so we wouldn’t have to do 1,000,000+ combinations of inputs and outputs) turning on more than one display at a time will crash the VCDsimulator. To see multiple displays on at once. Click the “Simulate POV” checkbox at the top of the screen in the “Set Signals” panel.Make a video showing these tests. When you click the center button, you should see a negative sign in the middle-right display and when you click the top button you should see all the displays blank. The Blanking only works with “simulate POV” unchecked.Deliverables The write up is very simple, just include the basic design process used to get the logic of the ALU, anything you had trouble with, an explanation of anything doesn’t work, etc. just a brief overview. Please answer the question how many hours of work did this project take you. Be sure to cite any references you use (such as the reference manual). References should be in IEEE-style format, here are some examples: Make sure everything is in a single PDF on the class page. You can join PDFs with Adobe Acrobat if you have multiple PDFs. Grading Write up /5 PointsPrintout of sevenSegMux.vhd (please paste a formatted and syntax highlighted copy your code here to format it: ) /10 PointsDemonstration of FPGA (either demo to the TA or instructor during recitation in person or make a video and post it on youtube depending on what your instructor says. Videos must be descriptive such as this example: ). /10 PointsBONUS Add another input to allow blanking of the rightmost digit. Describe the design and changes required in a separate section of the write up and a graphic of the changed FSM and describe changes to the top and constraints file. Show this in your video. /2 Points /Total of 25 Points Appendix A: Testbench code. Adjust to the name of your sevenSegment Mux entity and inputs and output names.LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx leaf cells in this code.--library UNISIM;--use UNISIM.VComponents.all;ENTITY displayMux_tb ISEND displayMux_tb;ARCHITECTURE Behavioral OF displayMux_tb ISSIGNAL clk : std_logic;SIGNAL sw : std_logic_vector(15 DOWNTO 0);SIGNAL btns : STD_LOGIC_VECTOR(4 DOWNTO 0); --order of button is btnU, btnR, btnD, btnL, btnC SIGNAL seg : std_logic_vector(0 TO 6);SIGNAL an : std_logic_vector(3 DOWNTO 0);COMPONENT sevenSegMux ISPORT (clk : IN STD_LOGIC;in0 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);in1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);in2 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);in3 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);blank : IN STD_LOGIC;neg : IN STD_LOGIC;an : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);seg : OUT STD_LOGIC_VECTOR (0 TO 6));END COMPONENT;BEGINsevenSegMux_insta0 : sevenSegMux PORT MAP(clk => clk,in0 => sw(15 DOWNTO 12),in1 => sw(11 DOWNTO 8),in2 => sw(7 DOWNTO 4),in3 => sw(3 DOWNTO 0),blank => btns(0), --btnUneg => btns(4), --btnCseg => seg,an => an);-- This counts each set of switches one at a time only -- because the VCD output file would be massive otherwise.-- Once 0x0 throught 0xF have been displayed on each 7-segment individually, -- it will test the blanking and negative sign feature. -- When testing with the VCDSimulator, make sure not to activate -- any cases that aren't defined here. For instance, if you -- enter 0x0011 on the switches, or press the buttons when-- a number other than "0000" is being displayed it'll crash -- since we never simulated those values on the inputs. clock_increment : --This will change the state and show which 7-segment is on at a time.clk <= '0','1' AFTER 160ns,'0' AFTER 165ns,'1' AFTER 310ns,'0' AFTER 315ns,'1' AFTER 480ns,'0' AFTER 490ns,'1' AFTER 630ns;Switch_increments :--test state 0 inputssw(15 DOWNTO 12) <= "0000", "0001" AFTER 10ns, "0010" AFTER 20ns, "0011" AFTER 30ns,"0100" AFTER 40ns, "0101" AFTER 50ns, "0110" AFTER 60ns, "0111" AFTER 70ns,"1000" AFTER 80ns, "1001" AFTER 90ns, "1010" AFTER 100ns, "1011" AFTER 110ns,"1100" AFTER 120ns, "1101" AFTER 130ns, "1110" AFTER 140ns, "1111" AFTER 150ns,"0000" AFTER 160ns;--test state 1 inputssw(11 DOWNTO 8) <= "0000", "0001" AFTER 160ns, "0010" AFTER 170ns, "0011" AFTER 180ns,"0100" AFTER 190ns, "0101" AFTER 200ns, "0110" AFTER 210ns, "0111" AFTER 220ns,"1000" AFTER 230ns, "1001" AFTER 240ns, "1010" AFTER 250ns, "1011" AFTER 260ns,"1100" AFTER 270ns, "1101" AFTER 280ns, "1110" AFTER 290ns, "1111" AFTER 300ns,"0000" AFTER 310ns;--test state 2 inputssw(7 DOWNTO 4) <= "0000", "0001" AFTER 310ns, "0010" AFTER 320ns, "0011" AFTER 330ns,"0100" AFTER 340ns, "0101" AFTER 350ns, "0110" AFTER 360ns, "0111" AFTER 370ns,"1000" AFTER 380ns, "1001" AFTER 390ns, "1010" AFTER 400ns, "1011" AFTER 410ns,"1100" AFTER 420ns, "1101" AFTER 430ns, "1110" AFTER 440ns, "1111" AFTER 450ns,"0000" AFTER 460ns;button_increments :btns <= "00000","00001" AFTER 460ns,"10000" AFTER 470ns,"10001" AFTER 480ns,"00000" AFTER 490ns; --activates btnU and btnC in order.--test state 3 inputssw(3 DOWNTO 0) <= "0000", "0001" AFTER 490ns, "0010" AFTER 500ns, "0011" AFTER 510ns,"0100" AFTER 520ns, "0101" AFTER 530ns, "0110" AFTER 540ns, "0111" AFTER 550ns,"1000" AFTER 560ns, "1001" AFTER 570ns, "1010" AFTER 580ns, "1011" AFTER 590ns,"1100" AFTER 600ns, "1101" AFTER 610ns, "1110" AFTER 620ns, "1111" AFTER 630ns,"0000" AFTER 640ns;END Behavioral; ................
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