Embedded Design Flow Workshop
System Design Flow on Zynq using Vivado WorkshopZedBoardCOURSE DESCRIPTIONThis course provides professors necessary skills to design?and debug a system using Vivado IP Integrator, hardware analyzer, and Vivado HLS.Install Xilinx softwareProfessors may submit the online donation request form at to obtain the latest Xilinx software. The workshop was tested on a PC running Microsoft Windows 7 professional edition. Vivado 2015.2 System EditionDownload and install software driver, for serial communication using micro-USB cable, available at Setup hardwareConnect ZedBoard Connect programming cable between configuration port of ZedBoard and PCConnect another micro USB cable between ZedBoard’s UART port and PC USB portConnect the power supply and power on the boardInstall distribution Extract the 2015_2_zynq_zedboard_sources.zip file in the c:\xup\sys_design directory. This will create a 2015_2_zynq_sources folder. Create the c:\xup\sys_design\2015_2_zynq_labs directory. This is where you will do the labs. The 2015_2_zynq_labdocs_pdf.zip file consists of lab documents in the PDF format. Extract this zip file in the c:\xup\sys_design directory or any other directory of your choice.For Professors onlyDownload the 2015_2_zedboard_labsolution.zip and 2015_2_zynq_docs_source.zip files using your membership account. Do not distribute them to students or post them on a web site. The 2015_2_zynq_docs_source.zip file contains lab documents in Microsoft Word and presentations in PowerPoint format for you to use in your classroom.Get StartedReview the presentation slides (see course agenda) and step through the lab exercises (see lab descriptions) to complete the labs.COURSE AGENDADay 1 AgendaDay 1 MaterialsClass Intro01_class_intro.pptx7 Series Architecture Overview 11_7_Series_Architecture_Overview.ppt xVivado Design Flow12_Vivado Design_Flow.pptxLab 1: Synthesizing a RTL Design 11a_lab1_intro.pptxLab01.docxXilinx Design Constraints13_Xilinx_Design_Constraints.pptxLab 2: Xilinx Design Constraints13a_lab2_intro.pptxLab02.docxIP Integrator and Embedded System Design Flow14_IPI_And_Embedded_System_Design.pptxLab 3: Create a Processor System using IP Integrator14a_lab3_intro.pptxLab03.docxDay 2 AgendaDay 2 MaterialsCreating and Adding Custom IP21_Creating_and_Adding_Custom_IP.pptxLab 4: Creating and Adding Custom IP in PL21a_lab4_intro.pptxLab04.docxSystem Debugging22_System_Debugging.pptxLab 5: System Debugging using Vivado Logic Analyzer and SDK22a_lab5_into.pptxLab05.docxProfiling and Performance Improvement23_Profiling_and_Performance_Improvement.pptxIntroduction to High-Level Synthesis with Vivado HLS24_Vivado_HLS_Intro.pptxImproving Performance and Resource Utilization25_Improving_Performance_and_Resource_UtilizationCreating an Accelerator26_Creating_an_accelerator.pptxLab 6: Creating a Processor System26a_lab6_into.pptxLab06.docxLAB DESCRIPTIONSLab 1 - Use Vivado IDE to create a simple HDL design. Simulate the design using the XSim HDL simulator available in Vivado design suite. Generate the bitstream and verify in hardware. Lab 2 - Create a project with I/O Planning type, enter pin locations, and export it to the RTL. Then create the timing constraints and perform the timing analysis. Lab 3 – Create a simple ARM Cortex-A9 based processor design targeting the ZedBoard using IP Integrator.Lab 4 - Use the Manage IP feature of Vivado to create a custom IP and extend the system with the custom peripheral. Write a basic C application to access the peripherals.Lab 5 - Insert various Vivado Logic Analyzer cores to perform cross-triggering and debug/analyze system behavior. Lab 6 - Profile an application performing a function both in software and hardware. Create an accelerator in Vivado HLS. Use the generated accelerator to build a complete system. Contact XUPSend an email to xup@ for questions or comments ................
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