Test Plan for CPM .ac.uk
FTM User Guide
(Production module PCB # PC3550M/2)
Contents:
Introduction and Layout
Typical Usage
Default link header settings
JTAG Programming of FPGA Configuration
Front panel detail
Ribbon Fibre Mapping
Default PLL frequencies
Link header description
Supply Voltage and Current monitoring
Version 1.3
Introduction
This document is intended as a quick-set-up guide and basic user manual focussing on the hardware side. Please refer to the FTM Specification for more detail.
The FTM is an ATCA based module that can be placed in either a hub or a node slot and perform functions appropriate to its position.
Be aware that the FTM will not supply clocks and TTC-info to logical slot3.
This was due to conflicting I/O requirements for its use in both Hub and Node slots.
This guide is for the Production FTM and not the Prototype version. Please be aware that some connectors have been changed or removed and identifiers (such as PL4) re-used for other types and functions. Production FTMs have serial numbers starting from 3.
Module Layout
[pic]
Usage
FTM in a Hub slot.
The FTM may be placed in Hub1 slot to provide and mimic a subset of the functionality of a real Hub module. This allows early initial testing of FEX modules in a simplified environment.
An FTM in a Hub slot can distribute TTC clock and data information over the backplane to all Node slots except Node logical slot #3, and to the other Hub slot.
The FTM also provides a passive connection between its front panel and the backplane Ethernet ports of modules in Node slots 4 and 5.
Note that the FTM’s Data Source and Sink functions are available while operating in a Hub Slot.
A typical set-up with one FTM and one eFEX in an ATCA shelf is shown below:
[pic]
The FTM also receives the readout links from modules in slots 4 and 5. This connection is useful for performing IBERT tests on the readout hardware.
The master clock on the FTM can either be selected from an on-board 40.08 MHz crystal oscillator, or from a TTC-FMC card if fitted. The TTC-FMC has a fibre-optic receiver that can connect to the legacy TTC system.
Clock source options PL14 *:
TTC-FMC: Remove all links
LEMO in: link 1 - 2
On-board XTAL: link 3 - 4
* FTM will automatically select a clock from the backplane when placed in a Node slot, unless over-ridden by adding a link to PL4. See section below.
FTM in a Node slot.
When placed in a Node slot, the FTM receives TTC clock and data information over the backplane from Hub slot1. The IPBus interface is also connected to the backplane when placed in a Node slot.
A typical set-up with two FTMs in Node slots connected to an eFEX is shown below:
[pic]
Over-ride of Automatic Node / Hub selection
The selection between Hub and Node operation is automatic, but certain functions used for Hub operation may be re-enabled in a Node slot by adding links to header block PL4. For example, the Ethernet connection for IPBus can be permanently connected to the front panel RJ45 connector by adding a link across pins 11 – 12.
Also that an FTM placed in Hub slot 2 will not behave like a Hub module unless links are added to PL4. For example, to drive a TTC clock onto backplane, link 5 – 6.
Note PL4 on Prototype FTM is a different header to one described here. The part was removed and the identifier re-used for the Production version.
PL4 links:
12 – 11 = IPBus to use Ethernet on front RJ45 connector
10 – 9 = IPMC to use Ethernet on front RJ45 connector
8 – 7* Use on-board TTC clock source ie.TTC-FMC
6 – 5* Enable TTC clock onto backplane
4 – 3 = Select TTC-Info onto backplane for other Hub slot.
2 – 1 = Unused spare signal to Control FPGA.
Pin 1 is nearest to module bottom edge.
* Note linking either 6 – 5 or 8 – 7 will activate both functions due to a design error on the schematic.
Default / Preferred link settings for ‘normal’ operation.
PL34 link 1-2 Enable front panel ON switch
(If no IPMC)
PL23 link 1-2 Vcc_adj delay. From VCCAUX.
PL25 link 3-4 Vcc_adj voltage. Sets Vcc_adj to 2.5V.
PL24 link 1-2, F/P button re-configures all FPGAs
3-4, This adds a needed power-on delay
5-6
PL30 link open Drive JTAG from connector PL32
PL26 link 1-2 Sets Ethernet Phy interface to GMII
PL27 link 1-2
Ethernet Address
MAC address
The MAC address is based upon the FTM serial number as provided by an EEPROM attached to the Control FPGA.
mac_address Hardware Manager -> Open Target -> Auto Connect
The JTAG connected devices appear in the following order:
Marvell PHY
XC7K325T – Control FPGA ( -2 in FFG900 package )
XC7VX415T – DSS1 FPGA ( -2 in FFG1158 package )
XC7VX415T – DSS2 FPGA ( -2 in FFG1158 package )
To load bit-file into it’s configuration memory, Right-click on the FPGA and select Add Configuration Memory Device
Filter for: Spansion, 256, SPI, All. Select Part S25FL256sxxxxx0
Configuration files will be found at: efex.web.cern.ch/efex/firmware/FTM/official
These are in the ‘.bin’ format, file name indicating version ie:
FTM_Control_v0.0.22.bin
FTM_DSS_ v0.0.22.bin
For debug purposes there may also be some .ltx files for driving ila and vio core.
Front panel Details
Power-on Switch
Front panel Toggle switch near lower handle.
Down position = ON (if enabled by PL34)
LEDs
[pic]
Connectors
[pic]
SK5 Dual LEMO: BGO out (NIM), Inhibit out (NIM)
SK8 Dual LEMO: Orbit out (NIM* / ECL), L1A out (NIM* / ECL)
The above requires ‘level conversion’ daughter cards in positions SK47 - SK50.
Allows external logic level (and direction) to be changed if needed in the future.
*Note as of June 2020, only cards with NIM level outputs have been made and fitted.
SK11 Dual LEMO: 40MHz clock in (50 Ω), BUSY in (TTL)
SK14 Dual LEMO: 40MHz clock out (50 Ω source + AC coupled),
DSS Refclock0 / 1 monitor
PL12 IDC Header 2 x 8: Trigger Type inputs (Differential ECL) pinout as per TTCvi
MGT to MiniPOD and MTP optical connector mapping
DSS MGTs are grouped into Quads with three Quads connecting to one 12 channel MiniPOD transmitter/receiver.
Within each quad, connectivity from FPGA to MiniPOD is not regular, but as needed to optimise PCB routing.
DSS playback memory is arranged into 48 separate blocks of RAM. The RAM blocks are ordered in address space as per their MGT Tx channel name ie 114/0, 114/1, 114/2, 114/3, 115/0 … 219/3.
DSS1 MGT Tx connections
|MiniPOD #: |OC3 |OC4 |OC9 |OC10 |
| | | | | |
|MiniPOD |Driven by |Driven by |Driven by |Driven by |
|channel # | | | | |
|0 |Q114_TX2 |Q117_TX2 |Q214_TX2 |Q217_TX2 |
|1 |Q114_TX0 |Q117_TX1 |Q214_TX0 |Q217_TX1 |
|2 |Q114_TX3 |Q117_TX3 |Q214_TX3 |Q217_TX3 |
|3 |Q114_TX1 |Q117_TX0 |Q214_TX1 |Q217_TX0 |
|4 |Q115_TX2 |Q118_TX2 |Q215_TX2 |Q218_TX2 |
|5 |Q115_TX1 |Q118_TX1 |Q215_TX0 |Q218_TX0 |
|6 |Q115_TX3 |Q118_TX3 |Q215_TX3 |Q218_TX3 |
|7 |Q115_TX0 |Q118_TX0 |Q215_TX1 |Q218_TX1 |
|8 |Q116_TX3 |Q119_TX3 |Q216_TX3 |Q219_TX3 |
|9 |Q116_TX0 |Q119_TX0 |Q216_TX0 |Q219_TX0 |
|10 |Q116_TX2 |Q119_TX2 |Q216_TX2 |Q219_TX2 |
|11 |Q116_TX1 |Q119_TX1 |Q216_TX1 |Q219_TX1 |
Each DSS FPGA, via its associated four MiniPODs, is connected to their individual 48 way MTP optical connector using 12 way ribbon cables.
Note that the fibre numbering runs in reverse order to that of the MiniPOD channels,
so for example MTP fibre1 connects to MiniPOD OC3 channel #11.
The fibre numbering is as defined in the FOX documentation.
The diagram below shows the numbering of the fibres as per the FOX documentation for the FOX type ‘D’ MTP48 connector.
[pic]
DSS1 MGT Rx connections
Note the receiver mappings are different to those of the transmitter.
|MiniPOD #: | OC6 |
| | |
|MiniPOD |Received by |
|channel # | |
|0 |Q114_RX1 |
|1 |Q114_RX2 |
|2 |Q114_RX0 |
|3 |Q114_RX3 |
|4 |Q115_RX3 |
|5 |Q115_RX1 |
|6 |Q115_RX0 |
|7 |Q115_RX2 |
|8 |Q116_RX0 |
|9 |Q116_RX3 |
|10 |Q116_RX1 |
|11 |Q116_RX2 |
A 12 way MTP connector is used to connect to the single MiniPOD receiver of each DSS FPGA. As with the transmitter connection, the MTP numbering order as given in the FOX documentation runs opposite to the channel number of the MiniPOD receivers.
[pic]
DSS2 mappings
DSS2 has an identical mapping to that of DSS1.
For DSS2, MiniPODs OC1, OC2, OC7, OC8 and OC5 are used instead of OC3, OC4, OC9, OC10 and OC6 respectively.
Default PLL Frequencies
DSS Refclock0s are sourced by PLL#2 and has a default frequency of 160MHz.
DSS Refclock1s are sourced by PLL#3 and has a default frequency of 280MHz.*
* One exception is Quad 219 Refclock1 which is sourced by PLL#1 with a 160 MHz Refclock1 for the optional TTC-INFO input on the DSSs from Control FPGA.
PLL output frequencies in MHz
|PLL#\Output: |Q0 |Q1 |
|PL34 |2 |Allow power-up from front-panel switch. |
| | |Remove when IPMC working |
|PL23 |37 |VCC_ADJ power-on delay control |
|PL25 |37 |Sets FMC VCC_ADJ supply voltage (1.2, 1.8, 2.5 or 3.3V) |
|PL24 |7 |Connects Front panel Reconfigure Push-switch ,with power-on delay, to each FPGA |
|PL14 |27 |Module clock source (XTAL, LEMO or TTC-FMC) |
|PL30 |32 |JTAG master ( PL32 Header or IPMC) |
|PL26, |6 |Ethernet Phy Transceiver configuration |
|PL27, | | |
|PL28 | | |
|PL9, |19, |DSS FPGA Spare pins. Pin 5 now identifies FPGA location. |
|PL10 |12 | |
|PL18, |6 |FMC I2C routing |
|PL19 | | |
|PL20 |6 |FMC VAUX selection |
|PL6 |7 |Ethernet MAC(?) address: link to force IP Address to known # |
|PL22 |4 |IPMC test connection |
|PL32 |32 |JTAG access connector |
|PL31 |2 |ATCA PSU Trim control (as yet unused) |
|PL1, |37 |FAN 12V power cable connector |
|PL2, | |(for when module used on test-bench) |
|PL21 | |Note pin-out may be reversed to standard PC fan. |
|PL35 |4 |Connector for Front-panel ejector handle switch for IPMC |
|PL5 |29 |Select Front panel LEMO to Refclk0 (PLL2)/ Refclk1 (PLL3) |
Voltage and current monitoring points for debugging
|Signal |V Test-point |Voltage supplied| |I Test-point |Equivalent |Voltage at 100% rated|
| |name |V | |name |I/V factor Ω-1 |current |
|Payload 12V |TP28 |12.0 | | | | |
|MAN_3V3 |TP24 |3.3 | | | | |
|MAN_1V8 |TP17 |1.8 | | | | |
| | | | | | | |
|VCCINT_1V0 |TP11 |1.0 | |TP15 |20 | 2.5* |
|MGTAVCC_1VX |TP12 |1.05 | |TP16 |20 |1.5 |
|MGTAVTT_1V2 |TP8 |1.2 | |TP9 |5 |2.0 |
|MGTVCCAUX_1V8 |TP12 |1.8 | |TP7 |1 |1.5 |
| | | | | | | |
|VCC_1V8 |TP27 |1.8 | |TP26 |10 |1.6 |
|VCC_2V5 |TP23 |2.5 | |TP22 |10 |1.6 |
|VCC_3V3 |TP19 |3.3 | |TP18 |10 |1.6 |
| | | | | | | |
|VEE_3V3 |TP2 |- 3.3 | |TP1 |2 |0.7 |
|VCC_ADJ |TP13 |2.5 | |TP14 |2 |3.0 |
* ie. 2.5V = 50 Amps maximum rated current
In addition to the above, there is also a MMCX coaxial connector on each of the three MGT supply rails. This is for taking sensitive noise measurements using an oscilloscope. Each connector has an inline 100nF DC blocking capacitor.
MGTAVCC SK2
MGTAVTT SK3
MGTVCCAUX SK4
-----------------------
PLL Status + Configuration Done LEDs (PLL0, DSS2, DSS1, Control)
DSS1
DSS2 Tx
DSS1 Tx
DSS2 Rx
DSS1 Rx MTP12
Force
IPAddr.
Clock
Select
DSS2
MiniPODs
Control
FPGA
TTC-FMC
Node/Hub Over-ride
JTAG
on/off
FTM
eFEX
IPBus
Backplane - Base
Rear Fibre
Readout
TTC
Clock +
TTC Info
Hub 2
Hub 1
Node 3
Node 4
FTM
FTM
eFEX
IPBus
Rear Fibre
Clock +
TTC Info
Node
Node
Node
Backplane
Front-panel
SK11 (LEMO)
Backplane
Clock Rx
40.08 MHz
XTAL Osc.
Clock_select (PL14)
Backplane TTC - Clock
Primary PLL Jitter Cleaner +
Multiply
CDCE62005
PLL0
Fanout
CDCLVP111
TTC-FMC Clock
To other PLLs
40 MHz
Front-panel
SK14 (LEMO)
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