Test Plan for CPM .ac.uk
FTM Commissioning Guide (1 of 2)
Production Module (pc3550m2)
Contents:
Introduction
Commissioning
Component check prior to first power-on
Check for Supply Shorts
Fitting Links
Power-up Voltage Checks
JTAG connection
Configuration Flash access
PLL Programming
TTC-FMC Operation
MGT Local loop-back checks
MiniPOD connections
Backplane Connections
Handover to Software-driven testing
Introduction
The FTM is an ATCA based module that can be placed in either a hub or a node slot and perform functions appropriate to its position. Its function is as a test module for commissioning the L1Calo *FEX processing modules. Any reference to the module’s position in the ATCA shelf is in terms of its logical slot number.
Prior to assembly, the bare PCB will have been checked for the correct impedance values on its high-speed multi-gigabit signal carrying tracks.
The purpose of these tests is to check the assembly of the module as soon as it is received from the manufacturer, so that any problems can be dealt with immediately.
Module Layout
[pic]
Results will be recorded on a separate sheet for each FTM.
(1) Component checks, Modifications and pin-header set-up prior to first power-up
Modifications to PCB
Resistor R433 Removed (UVLO MGTAVCC)
Capacitor 2.5V 2700uF added across capacitor C231 (on MGTAVCC)
Check for Supply Shorts
On-board module supplies
Check for shorts across power rails to ground. Take ground connection from any of the ground bars. Consider resistance > 10Ω a pass. Test-points are:
TP28, TP24, TP11, TP12, TP8, TP6, TP27, TP23, TP19, TP2, TP13.
Check DC/DC converters Voltage Setting resistors.
Enter the values measured into the table at the end of the document.
|Pin to 0V unless stated |Resistor fitted |Typical Measurement |Actual Measurement |
|U2 pin 4 to pin 1 |R164 = 220k |27k | |
|U23 pin 8 |R256 = 12.1K |6.1k | |
|U69 pin 18 to pin 4 |R422 = 63.4k |38.6k | |
|U70 pin 12 |R421 = 63.4k |26.3k | |
|U74 pin 5 to PL25 pin 4 |R104 = 4.2k |4.2k | |
|U90 pin 8 |R458 = 1.21k |1.09k | |
|U96 pin 8 |R486 = 2.37k |1.96k | |
|U104 pin 8 |R505 = 4.75k |3.38k | |
Set following links prior to power-up and JTAG tests
PL34 link 1-2 Enable front panel ON switch
PL23 link 1-2 Vcc_adj delay. From VCCAUX.
PL25 link 3-4 Vcc_adj voltage. Sets Vcc_adj to 2.5V.
PL24 link 1-2 FPGA Configuration
link 3-4 F/P button re-configures all FPGAs
link 5-6 Power-on configuration delay
PL14 link 3-4 Select clock source to on-board XTAL
PL30 link open Drive JTAG from connector PL32
PL26 link 1-2 Sets Ethernet MAC interface to GMII
PL27 link 1-2
Force MAC and IP address
PL6 link 1 – 2 to force ip address to set value of 192.168.200.1.
Normally IP address is a function defined in firmware based upon either the module serial number or the position of the module in the ATCA shelf.
(2) Power-up Voltage check
To be done on test-bench with desk fan. Do not fit IPMC at this stage.
Power-up.
Check all eight front-panel voltage indicators for are on for module FPGA supplies and for discrete logic supplies.
[pic]
DC/DC Converters
With voltmeter from 0V, check outputs of on-board supplies measured as follows:
Enter the values measured into the table at the end of the document.
|Signal |V Test point |Nominal Voltage /V |Acceptable limits /V |Measure |
| | | | |/V |
|Payload 12V |TP28 |12.0 |11.4 – 12.6 | |
|MAN_3V3 |TP24 |3.3 |3.20 – 3.40 | |
|VCCINT_1V0 |TP11 |1.0 |0.97 – 1.03 | |
|MGTAVCC_1VX |TP12 |1.05 |0.97 – 1.08 | |
|MGTAVTT_1V2 |TP8 |1.2 |1.17 – 1.23 | |
|MGTVCCAUX_1V8 |TP6 |1.8 |1.75 – 1.85 | |
|VCC_1V8 |TP27 |1.8 |1.71 – 1.89 | |
|VCC_2V5 |TP23 |2.5 |2.38 – 2.62 | |
|VCC_3V3 |TP19 |3.3 |3.14 – 3.46 | |
|VEE_3V3 |TP2 |- 3.3 |-3.14 - -3.46 | |
|VCC_ADJ |TP13 |2.5 |2.38 – 2.62 | |
FLASH VIO Shunt Regulators
Measure the FLASH RAM VIO supply on pin 14 of devices U36,U37 and U49 and record values in table at end of document.
Overvoltage detection potential-divider resistors
Overvoltage detector nominal sense values. Measure the potential divider voltages for nodes at LK11, LK40, LK42 – LK46 and record values in table at end of document.
Power-off
(3) JTAG Access to FPGA, FLASH and Configuration.
Test-bench with fan.
Check Module JTAG chain through FPGAs using Vivado
Connect Xilinx/Digilent cable to JTAG header PL32 located in lower front corner of PCB.
Power-up.
Using Vivado Hardware Manager.
Program and Debug -> Hardware Manager -> Open Target -> Auto Connect
Observe first FPGA is a XC7K325T which is the control FPGA,
Observe next two FPGAs, type XC7VX415T which are DSS1 then DSS2.
Load Control FPGA Configuration
Proceed to set-up Hardware Manager to access FLASH memory of Control FPGA.
Associate FLASH with FPGA by:
Right-click on FPGA and Add Configuration Memory Device
Filter for: Spansion, 256, SPI , All and select Part S25FL256sxxxxx0
Locate Configuration file, for example:
FTM_Control_v0.0.19.bin
Select Erase, Program and Verify.
Load Both DSS FPGA Configuration
For each DSS in turn, set-up Hardware Manager to access FLASH memory of FPGA.
Right-click on FPGA and Add Configuration Memory Device
Filter for: Spansion, 256, SPI , All and select Part S25FL256sxxxxx0
Locate Configuration file, for example:
FTM_DSS_ v0.0.19.bin
Select Erase, Program and Verify.
If programming is successful, close Vivado, Power-off and remove JTAG cable.
Check All FPGAs configure
Remember no heatsinks have been fitted at this stage so use a desk fan for cooling.
Power-on for only 10 seconds. This will be time enough to confirm the FPGAs have configured. The Control FPGA will configure first followed by the DSS FPGAs.
Confirm this by observing the Front Panel LEDs, one per FPGA DONE signal.
Power off after 10 seconds as FPGAs will begin to get very warm.
Fit Heatsinks
Fit type Farnell #1373252 (6.9 °C/W) to U62 (kintex-7)
Fit type Farnell #4302163 (123 °C/W) to U28, U29, U50 & U51 (PLLs 0 to 3)
Fit type Farnell #1373263 (4.3 °C/W) to U10 & U11 (virtex-7)
(4) Preliminary Software checks & PLL Load
ATCA Shelf.
Basic Ethernet Access
Test Ethernet interface to Control FPGA
If needed, Link PL6 to force IP address to known value of 192.168.200.1
Attach Ethernet cable to front panel SK36
Check DUP and 1G LEDs light
Ping IP address for response. Check Rx and Tx LEDs flash
Test IPBus F/W in Control FPGA is responding
Check ID register present
For each DSS, Test IPBus F/W communication with DSS FPGAs
Check ID register present
Program PLLs and check lock status
Check for presence of four PLLs on SPI bus. example PLL0:
cd to directory with PLL configuration files, then:
python ~/python/loadPLL.py --ReadPLL -n 0
Run script to program these PLLs. example PLL2:
python ~/python/loadPLL.py --LoadPLL -n 2 -f CDCE62005_PLL2.ini
python ~/python/loadPLL.py --BurnPLL -n 2
Reload PLL from its EEPROM, by either cycling module power or by toggling
PLL_PD bit (PLL Power Down) in Module_Control -> Control register.
Check front panel LED for PLL0 is on.
Check PLLs are locked by reading status register. ie Using Serendip:
CFPGA -> Module_Control -> Status -> PLL*Lock bits (9 – 6)
TTC-FMC Connections
Plug-in TTC-FMC module, connect a TTC fibre and remove PL14 link.
With an Idle TTC feed, check TTC Lock and PLL lock status and examine TTC data and clock transitions using F/W with TTC ILA. A repeating pattern of “00101101” should be seen.
(5) Clock Distribution and MGT Stability
ATCA Shelf or Test-Bench with fan using Oscilloscope.
Check PLL clock testpoints:
SK29 is 40MHz (PLL0)
SK28 is 160MHz (PLL1)
SK25 is 160MHz (PLL2)
SK26 is 140MHz (PLL3)
Check Refclock1 distribution
SK24 and SK22 is 280MHz
Refit JTAG cable.
Test Control FPGA MGTS in Near-end PMA loopback
Using Vivado Hardware Manager, load IBERT firmware.
(example_ibert_con_115_8_4ref1_6g4.bin)
and manually connect links if needed
Check all internal MGT PLLs are locked
Check all 16 links lock with NE PMA loopback
Test DSS FPGA MGTS in Near-end PMA loopback
Load 12 channel IBERT firmware to each DSS FPGA via JTAG such as
IBERT_114_116.bin
Check all internal MGT PLLs are locked
Check all 12 links lock with NE PMA loopback
(6) Test MiniPOD DSS FPGA Connections
ATCA Shelf or Test Bench with fan
Requires JTAG cable and Vivado HW Manager.
Using one MiniPOD Rx , One MiniPOD Tx connected via 12way optical ribbon assembly with MiniPOD Prizm terminators.
With a Rx MiniPOD fitted to one DSS FPGA, place a Tx MiniPOD in turn at each of 4 Tx sites of the other DSS FPGA. For each of 4 Tx sites, load IBERT as appropriate for Transmitting DSS and then load IBERT for MGTs 114 – 116 on receiving DSS.
For example,
Use MiniPOD Rx in OC6 and run IBERT_114_116 on DSS1
Use MiniPOD Tx in OC1 and run IBERT_114_116 on DSS2.
then
Use MiniPOD Tx in OC2 and run IBERT_117_119 on DSS2.
then
Use MiniPOD Tx in OC7 and run IBERT_214_216 on DSS2.
then
Use MiniPOD Tx in OC8 and run IBERT_217_219 on DSS2.
[pic]
(7) Test Control FPGA Backplane connections
ATCA Shelf with another FTM
Requires JTAG cable and Vivado HW Manager, and another FTM.
Place one FTM in Slot1 with another FTM in Slot4 and then in Slot5
Setup IBERT on both modules and check the following 12 receivers lock
Channels 8, 10 – 14 ( = MGT X0Y8 , MGT X0Y10 … ) for receiving Slot4.
Channels 0, 2 – 6 ( = MGT X0Y0 , MGT X0Y2 … ) for receiving Slot5.
Note this also tests six transmission connections of the other FTM to Hub1.
For the FTM in Slot4 (and then in Slot5) using IBERTcheck the following receiver lock
Channels 1 ( = MGT X0Y1 )
Note this also tests the TTCInfo MGT Tx of FTM in HUB1 and fan-out to Slots 4 & 5.
Note if using a 3Gb/s backplane, IBERT may report a few errors in 1012 bits.
Handover to Software based tests
Ensure the latest production firmware is loaded into all FPGAs.
Typical Configuration bit-files used (as of May 2020) will be found at: efex.web.cern.ch/efex/firmware/FTM/official
These are in the ‘.bin’ format, file name indicating version ie:
FTM_Control_v0.0.19.bin
FTM_DSS_ v0.0.19.bin
Remember to remove Link PL6 which forces IP address to a fixed value.
Appendices
Description of other pin header functions
PL14: Local Clock source options
Select TTC-FMC: No links
Select LEMO in: link 1 - 2
Select on-board xtal: link 3 - 4
PL4: Debug options
Link 3 – 4 Drive Hub Clock and Data on ‘specific pins’, otherwise Node data
Link 5 – 6 Use Local clock as master for FTM, otherwise use Backplane clock
Link 9 – 10 Use Front panel RJ45 for IPMC, otherwise use backplane
Link 11 – 12 Use Front panel RJ45 for IPBus, otherwise use backplane
Location of DC/DC Vset Resistors
U2 & U23
[pic] [pic]
U69 , U70 & U74
[pic]
U90, U96 & U104
[pic]
Location of Voltage test-points and default links
[pic]
[pic]
Record Sheet FTM S# …..
Date …..
(1) Component Checks
|PCB Modifications done | |
|Supply Shorts Check | |
|Header Links fitted | |
DC/DC Vset Resistors. Values recorded below:
Consider within 10% a pass. The measurement includes Vset resistor in parallel with a network of resistors and semiconductors so measured resistance will be lower than that of just the Vset resistor
|Pin to 0V unless stated |Resistor fitted |Typical Measurement |Actual Measurement |Pass |
|U2 pin 4 to pin 1 |R164 = 220k |29k | | |
|U23 pin 8 |R256 = 12.1K |6.1k | | |
|U69 pin 18 to pin 4 |R422 = 63.4k |38.6k | | |
|U70 pin 12 |R421 = 63.4k |26.3k | | |
|U74 pin 5 to PL25 pin 4 |R104 = 4.2k |4.2k | | |
|U90 pin 8 |R458 = 1.21k |1.09k | | |
|U96 pin 8 |R486 = 2.37k |1.96k | | |
|U104 pin 8 |R505 = 4.75k |3.38k | | |
(2) Power-up Voltage checks
|Power-on LEDs | |
On-board Supply Voltages. Values recorded below:
With voltmeter, check outputs of on-board supplies measure as follows:
|Signal |V Test point |Nominal Voltage /V |Acceptable limits /V |Measure | |
| | | | |/V |Pass |
|Payload 12V |TP28 |12.0 |11.4 – 12.6 | | |
|MAN_3V3 |TP24 |3.3 |3.20 – 3.40 | | |
|VCCINT_1V0 |TP11 |1.0 |0.97 – 1.03 | | |
|VCC_2V5 |TP23 |2.5 |2.38 – 2.62 | | |
|VCC_3V3 |TP19 |3.3 |3.14 – 3.46 | | |
|VEE_3V3 |TP2 |- 3.3 |-3.14 - -3.46 | |
|U36 |1.8 |1.71 – 1.89 | | |
|U37 |1.8 |1.71 – 1.89 | | |
|U49 |2.5 |2.37 – 2.63 | | |
Overvoltage dividers. Values recorded below:
| |Nominal V |Measured V |
|LK43 |0.80 | |
|LK44 |0.80 | |
|LK42 |0.80 | |
|LK40 |0.80 | |
|LK11 |0.80 | |
|LK45 |0.80 | |
|LK46 |0.81 | |
(3) JTAG Access & FPGA Configuration
JTAG Chain
| |Pass |
| All FPGAs Visible | |
| Control FLASH Programmed | |
| DSS1 FLASH Programmed | |
| DSS2 FLASH Programmed | |
FPGA Configuration
| |Pass |
|Control Configured | |
|DSS1 Configured | |
|DSS2 Configured | |
(4) Preliminary Software checks & PLL Load
Ethernet Access
| |Pass |
|Ping | |
|Control ID Register read | |
|DSS1 ID Register read | |
|DSS2 ID Register read | |
PLL Programming
| |Pass |
|Read PLLs 0 – 3 | |
|Program PLLs 0 – 3 | |
|PLLs Locked | |
TTC-FMC Operation
| |Pass |
|TTC lock (front LED) | |
|PLL lock (front LED) | |
|TTC Idle seen on ILA | |
(5) Clock Distribution and MGT Stability
Clock distribution
|Connector |Pass |
|SK29 is 40MHz (PLL0 output) | |
|SK28 is 160MHz (PLL1 output) | |
|SK25 is 160MHz (PLL2 output) | |
|SK26 is 140MHz (PLL3 output) | |
|SK24 is 280MHz (Refclock1) | |
|SK22 is 280MHz (Refclock1) | |
Basic MGT Stability
|FPGA |Pass |
|Control, all 16 MGTs with NE PMA locked | |
|DSS1, all 48 MGTs with NE PMA locked | |
|DSS2, all 48 MGTs with NE PMA locked | |
(6) Test MiniPOD Connections
A pass is all 12 Rxs of each MiniPOD recording BERT with 0 errors in 1012
|DSS1 Tx |DSS2 Rx |Pass |
|OC3 |OC5 | |
|OC4 |OC5 | |
|OC9 |OC5 | |
|OC10 |OC5 | |
|DSS2 Tx |DSS1 Rx |Pass |
|OC1 |OC6 | |
|OC2 |OC6 | |
|OC7 |OC6 | |
|OC8 |OC6 | |
(7) Test Control FPGA backplane connections
Using FTM S# …
|Position |Pass |
|Slot 1, all 12 incoming MGT links locked (Readout Rx) | |
|Slot 1, both TTCINFO links locked (TTCINFO TX) | |
|Slot 4, all 6 outgoing MGT links locked (Readout Tx) | |
|Slot 4, TTCINFO link locked (TTCINFO Rx) | |
Comments
-----------------------
JTAG
TTC-FMC
Control
FPGA
Power Supplies
DSS1
DSS2
on/off
PL34 link
Configured FPGAs
FPGA Supplies
Logic
Supplies
Ethernet
Status
IPMC
Status
Module
Status
ATCA
Power
PLL0 DSS2 DSS1 CON
1V0 1V8 1V2 1VX
2V5 3V3 1V8 VEE
TX RX DUP 1G
Y G R B
PLLs Err Node Hub
O/V INT BOK AOK
Module’sInternal
supplies
-3.3V
1.8V
1.2V
1.0V
1.05V
3.3V
12.0V
1.8V
2.5V
3.3V
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