Embedded Design Flow Workshop - Xilinx



High-Level Synthesis Flow on Zynq using Vivado HLS WorkshopPYNQ-Z1/Z2COURSE DESCRIPTIONThis course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. After completing this workshop, you will be able to understand high-level synthesis flow of Vivado HLS, apply appropriate directives to optimize design performance, and create a custom peripheral and add it to a processor system.?Install Xilinx softwareProfessors may submit the online donation request form at to obtain the latest Xilinx software. The workshop was tested on a PC running Microsoft Windows 10 professional edition. Vivado 2018.2Vivado HLS 2018.2Setup hardwareConnect PYNQ-Z1/Z2 Set the power supply jumper to USB so the board can be powered up and laboratory assignments can be carried out using single micro-usb cableConnect micro USB cable between PROG UART port of the board and PCYou will also need Micro-SD card adaptor.Install distribution Git clone the repository using the following command:git clone High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS.git Copy the source directory as 2018_2_zynq_docs_sources in the c:\xup\hls directory. Create the c:\xup\hls\labs directory. This is where you will do the labs. The labdocs in markdown format are located in the cloned directory. They can also be accessed at Professors onlyDownload the 2018_2_zynq_docs_source.zip file using your membership account. Do not distribute them to students or post them on a web site. The 2018_2_zynq_docs_source.zip file contains presentations in PowerPoint format for you to use in your classroom.Get StartedReview the presentation slides (see course agenda) and step through the lab exercises (see lab descriptions) to complete the labs.COURSE AGENDADay 1 AgendaDay 1 MaterialsClass Intro01_class_intro.pptxIntroduction to High-Level Synthesis11_HLS_Intro.ppt xUsing Vivado HLS12_Using_VivadoHLS.pptxLab 1: Vivado HLS Design Flow 12a_lab1_intro.pptx01_Lab.docxImproving Performance13_Improving_Performance.pptxLab 2: Improving Performance13a_lab2_intro.pptx02_Lab.docxData Types14_Data_Types.pptxDay 2 AgendaDay 2 MaterialsOptimizing for Area and Resources Utilization21_Improving_Resources.pptxLab 3: Improving Area and Resources Utilization21a_lab3_intro.pptx03_Lab.docxIO Protocols22_IO_Protocols.pptxCoding Considerations23_Coding_Considerations.pptCreating a Processor System24_Creating_Processor_System.pptxLab 4: Creating a Processor System to Filter Audio Signal24a_lab4_into.pptx04_Lab.docxLAB DESCRIPTIONSLab 1 - Experience a basic design flow of Vivado HLS and review generated output. Lab 2 - Use pipelining technique to improve performance. Lab 3 - Use directives to optimize resource sharing. Lab 4 - Use IP-XACT export capability of Vivado HLS to generate an IP and integrate the generated core in an embedded system developed using IP Integrator. Contact XUPSend an email to xup@ for questions or comments ................
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