California State University, Northridge



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ENROLLMENT FORM

SYNTHESIS Based ASIC Design

Methodology

Course fee $950 (CSUN Students - $800)

Check enclosed ? Make check payable to: CSUN Foundation

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|TEXT BOOK : Complete set of lecture notes, laboratory exercises and laboratory manual will be handed out. |

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|INSTRUCTORs : Ramin Roosta, Ph.D., Professor, CSUN |

|Taher Abbasi, MS, President, ByteK Designs, Inc. |

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|FEE : $950 per person |

|$800 for CSUN students |

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|LOCATION : The California State University, Northridge (CSUN) campus |

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|INSTRUCTOR BIOGRAPHY STATEMENT |

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|RAMIN ROOSTA, Ph. D., is a full time professor at College of Engineering and Computer Science, Department of Electrical and Computer Engineering, California |

|State University, Northridge (CSUN), California. Dr. Roosta has over 16 years experience in teaching and research related to Digital System Design Automation,|

|Design for testability and Top down design of Digital systems using VHDL. His two fellowships with JPL and several design clinics with industries center |

|around ASIC design and testing and fault tolerant Avionics systems. Dr. Roosta has been teaching Design Automation and VHDL related courses, such as Design |

|Automation of Digital Systems and VHDL Modeling, VHDL and Top-Down Design Methodology, Diagnosis and Reliable Design of Digital Systems, and Advanced Switching|

|theory at CSUN for a long period of time. Dr. Roosta has also been a consultant for Jet Propulsion Laboratory (JPL), Teledyne System Company, Northridge, CA,|

|Rockwell International, Litton Guidance and Control, Lockheed Martin, United Nations and several other Local and National Industries. |

|WEB Site , email ramin.roosta@csun.edu |

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|TAHER ABBASi is the president of Bytek Designs, Inc., and working on a project for one of the industry leading EDA companies in Sunnyvale, CA. He is also |

|currently teaching “Logic Synthesis using Synopsys” at UC Santa Cruz Extension. Prior to his present job, Taher has worked for Synopsys, Inc. in Mountain |

|View, CA for 4 years. He has worked with several Synopsys customers supporting the entire range of Synopsys tools, with special emphasis on the Test Compiler,|

|the Design Compiler, VHDL Compiler and Designware. Taher has contributed articles to “Impact” the Synopsys quarterly newsletter. His interests include the |

|Synopsys Behavioral Compiler and the development of methodologies using high-level design tools. He has also been on consulting assignments for Synopsys at |

|companies such as Intel Corporation in Portland, Oregon, Alcatel Network Systems in Dallas, Texas and 3COM in Santa Clara, CA. Taher has received the |

|prestigious “Friend of the Field” award at Synopsys for providing extraordinary support to the Synopsys Field Applications group. He completed his Masters in |

|Computer Engineering from California State University, Northridge, and his undergraduate in Electronics Engineering from Bombay University, India. Taher also |

|co-authored the books called “Logic Synthesis Using Synopsys” published by Kluwer Academic Publishers and “It’s the Methodology, Stupid!” published by ByteK |

|Designs, Inc. |

|WEB site , email taher@ |

|Interface Formats | |

|Example of SDF File | |

|Explanation of SDF File | |

|Example of EDIF File | |

|Explanation of EDIF File | |

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|INSTRUCTIONAL METHODS | |

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|Lecture with transparencies | |

|Group Project | |

|Class assignments (to be completed at student sites or CSUN site) | |

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|COURSE MATERIAL | |

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|Title : Top-down Design of Digital Systems Using VHDL | |

|Author : Dr. Ramin ROOSTA | |

|Publisher: California State University, Northridge, 1994 | |

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|Title : A Set of Design Examples Involving the Most | |

|Widely Used Digital Components in VHDL | |

|w/ Simulation And Synthesis Results | |

|Author : Dr. Ramin ROOSTA | |

|Publisher: California State University, Northridge | |

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|Complete Design examples of ATM and SRAM w/BIST Controller, along with | |

|Laboratory Manual | |

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|CLASSROOM, MEDIA, EQUIPMENT NEEDS | |

|Overhead projector and screen | |

|White Board | |

|EDA Lab equipped with Synopsys software | |

|Lab Research Assistant | |

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|PRE-REQUISITES FOR THE COURSE | |

|Some working knowledge of VHDL. | |

|Synthesis Based ASIC Design Methodology | |$950 | |

| |4 days | | |

| |(dates available upon request) |$800 CSUN Students | |

| | | | |

|Synthesis Based ASIC Design Methodology | |$950 | |

| |4 days | | |

| |(dates available upon request) |$800 CSUN Students | |

| | | | |

|Course Description |Topics of Discussion |

|This course covers the complete logic synthesis based ASIC design flow. The | |

|leading HDLs are clearly, VHDL and Verilog. The basics of VHDL and coding for |Brief Description of VHDL Coding Styles |

|simulation and synthesis of commonly used digital design blocks will be |Concurrent Statements |

|discussed. Also a comparison of some of the major differences between Verilog |Sequential Statements |

|HDL and VHDL shall be addressed. |Block Statements |

| |VHDL Textio |

|The overall design flow will be discussed with reference to the different CAD |Resolution Functions |

|tools used, with particular focus on the Synopsys logic synthesis tools. Key |Configuration Statements |

|aspects of the Synopsys Design Compiler such as, compiling a design from HDL |Packages |

|(VHDL or Verilog) to gates, characterization of sub designs, timing analysis, |Examples of Modeling common digital blocks |

|compilation strategies and applying constraints will be discussed in detail. |VHDL Behavioral Synthesis Techniques |

|Further, this course covers FPGA synthesis (FPGA Compiler) targeted to Xilinx |VHDL Behavioral Compiler |

|FPGA architectures, test synthesis (Test Compiler), Behavioral Compiler (BC), |VHDL and Verilog HDL: Comparison |

|back annotation and in-place optimization. It also introduces the basics of |Major Differences between VHDL and Verilog HDL |

|interface formats such as SDF, EDIF. |A few VHDL/Verilog Coding Examples |

| |Logic Synthesis Using Design Compiler |

| |HDL Synthesis Based ASIC Design Flow |

|Audience |Synthesizable VHDL/Verilog HDL Code Templates |

|This course is intended for design engineers, application engineers, CAD |Static Timing Analysis |

|engineers and engineering graduates interested in learning logic synthesis as |Setup Timing Check Reports |

|practiced in the real world. Also, Design and CAD Managers working towards |Hold Timing Check Reports |

|developing a logic synthesis based ASIC design methodology should benefit from |Multicycle Paths |

|this course. Familiarity with VHDL Language and syntax is recommended. |Functional False Paths |

| |Constraint and Optimizing Designs |

| |Time Budgeting |

|Course Motivation |Constraints Designs for Synthesis |

|Schematic capture based approach to Integrated Circuit (IC) design was |Hierarchical Compile |

|pioneered in the early eighties and was soon widely adopted. However, with |Characterize/Compile Approach |

|major advances in Electronic Design Automation (EDA) has emerged a relatively |In-Place Optimization |

|automated means of IC design, based on hardware description languages (HDL). |Synthesis Cost Function |

|The transition to HDL-based design has enabled a substantial increase in |FPGA Synthesis |

|productivity with regard to “gates per engineer per day” when compared to |Differences in ASIC and FPGA Synthesis |

|schematic capture based designs. Further, constant improvements in fabrication|Xilinx FPGA Synopsys Flow |

|technology have made possible ICs with over a million gates. At the center |Xilinx 4000 Architecture Summary |

|stage of this transition to HDL-based design lies “Logic Synthesis.” The ever |HDL Coding Suggestions for Xilinx |

|increasing demand to achieve highly complex, large gate count chips with a fast|Scan-Based Test Synthesis |

|turnaround has propelled synthesis to the forefront of the HDL-based ASIC |Scan Styles |

|design process. Logic synthesis has since become a fundamental component of |Partial Scan |

|the ASIC design flow. |Full Scan |

| |JTAG IEEE 1149.1 Standard |

| |Test Design Rules |

| |Test Synthesis Flow |

EDA & ASIC Laboratory

|Synthesis Based ASIC Design Methodology | |$950 |

| |4 days | |

| |(dates available upon request) |$800 CSUN Students |

| | | |

Home to EDA & Design Solutions

|Synthesis Based ASIC Design Methodology | |$950 | |

| |4 days | | |

| |(dates available upon request) |$800 CSUN Students | |

Mail check and enrollment form to:

Shirley Lang, Center for Research & Services

School of Engineering & Computer Science

California State University, Northridge

1811 Nordhoff Street

Northridge, CA 91330-8295

For more information, call (818) 677- 2146

or email: shirley.lang@csun.edu

or fax your enrollment form and payment

information to (818) 677- 2140

EDA & ASIC Laboratory

← Synthesis Based ASIC Design Methodology

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4 days

$950

(Please call Dr. Ramin Roosta for the dates and availability.

Course days are three weekdays and one weekend day

EDA and ASIC Design Lab

at CSUN

California State University, Northridge

1811 Nordhoff Street

Northridge, CA 91330-8295

Dr. Ramin Roosta (818) 677-2452, ramin.roosta@csun.edu



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