Si510/511 Crystal Oscillator (XO) 100 kHz to 250 MHz

Si510/511

CRYSTAL OSCILLATOR (XO) 100 kHZ TO 250 MHZ

Features

Supports any frequency from

3.3, 2.5, or 1.8 V operation

100 kHz to 250 MHz

Differential (LVPECL, LVDS,

Low jitter operation

HCSL) or CMOS output options

2 to 4 week lead times

Optional integrated 1:2 CMOS

Total stability includes 10-year

fanout buffer

aging

Runt suppression on OE and

Comprehensive production test

power on

coverage includes crystal ESR and Industry standard 5 x 7, 3.2 x 5,

DLD

and 2.5 x 3.2 mm packages

On-chip LDO regulator for power Pb-free, RoHS compliant

supply noise filtering

?40 to 85 oC operation

Applications

SONET/SDH/OTN Gigabit Ethernet Fibre Channel/SAS/SATA PCI Express

Description

3G-SDI/HD-SDI/SDI Telecom Switches/routers FPGA/ASIC clock generation

The Si510/511 XO utilizes Skyworks Solutions' advanced DSPLL technology to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO where a different crystal is required for each output frequency, the Si510/511 uses one fixed crystal and Skyworks Solutions' proprietary DSPLL synthesizer to generate any frequency across this range. This IC-based approach allows the crystal resonator to provide enhanced reliability, improved mechanical robustness, and excellent stability. In addition, this solution provides superior supply noise rejection, simplifying low jitter clock generation in noisy environments. Crystal ESR and DLD are individually production-tested to guarantee performance and enhance reliability. The Si510/511 is factory-configurable for a wide variety of user specifications, including frequency, supply voltage, output format, output enable polarity, and stability. Specific configurations are factory-programmed at time of shipment, eliminating long lead times and non-recurring engineering charges associated with custom frequency oscillators.

Functional Block Diagram

VDD

OE

Low Noise Regulator

Fixed Frequency Oscillator

Any-Frequency

0.1 to 250 MHz DSPLL? Synthesis

CLK+ CLK?

GND

Si5602

2.5x3.2mm

5x7mm and 3.2x5mm

Ordering Information: See page 14.

Pin Assignments: See page 12.

OE 1

4 VDD

GND 2

3 CLK

Si510 (CMOS)

NC 1

6 VDD

OE 2

5 CLK?

GND 3

4 CLK+

Si510(LVDS/LVPECL/HCSL/ Dual CMOS)

OOEE 11

66 VVDDDD

NNCC 22

55 CCLLKK??

GGNNDD 33

44 CCLLKK++

Si511(LVDS/LVPECL/HCSL/ Dual CMOS)

Skyworks Solutions, Inc. ? Phone [781] 376-3000 ? Fax [781] 376-3100 ? sales@ ? Rev. 1.4 ? Skyworks Proprietary Information ? Products and Product Information are Subject to Change Without Notice ? October 29, 2021

Si510/511

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . . 11 3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1. Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. Si510/511 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6. Package Outline Diagram: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. PCB Land Pattern: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 10. Package Outline Diagram: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11. PCB Land Pattern: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12. Package Outline Diagram: 3.2 x 5 mm, 6-Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 13. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 14. Package Outline Diagram: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 15. PCB Land Pattern: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 16. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 17. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

2

Skyworks Solutions, Inc. ? Phone [781] 376-3000 ? Fax [781] 376-3100 ? sales@ ?

Rev. 1.4 ? Skyworks Proprietary Information ? Products and Product Information are Subject to Change Without Notice ? October 29, 2021

Si510/511

1. Electrical Specifications

Table 1. Operating Specifications

VDD = 1.8 V ?5%, 2.5 or 3.3 V ?10%, TA = ?40 to +85 oC

Parameter Supply Voltage

Supply Current

Symbol

Test Condition

Min

Typ

Max

Unit

VDD

3.3 V option

2.97

3.3

3.63

V

2.5 V option

2.25

2.5

2.75

V

1.8 V option

1.71

1.8

1.89

V

IDD

CMOS, 100 MHz,

--

21

26

mA

single-ended

OE "1" Setting

VIH

OE "0" Setting

VIL

OE Internal Pull-Up/Pull-

RI

Down Resistor*

LVDS

--

19

23

mA

(output enabled)

LVPECL

--

39

43

mA

(output enabled)

HCSL

--

41

44

mA

(output enabled)

Tristate

--

--

18

mA

(output disabled)

See Note See Note

0.80 x VDD --

--

V

--

--

0.20 x VDD

V

--

45

--

k

Operating Temperature

TA

?40

--

85

oC

*Note: Active high and active low polarity OE options available. Active high option includes an internal pull-up. Active low option includes an internal pull-down. See ordering information on page 14.

Skyworks Solutions, Inc. ? Phone [781] 376-3000 ? Fax [781] 376-3100 ? sales@ ?

3

Rev. 1.4 ? Skyworks Proprietary Information ? Products and Product Information are Subject to Change Without Notice ? October 29, 2021

Si510/511

Table 2. Output Clock Frequency Characteristics

VDD = 1.8 V ?5%, 2.5 or 3.3 V ?10%, TA = ?40 to +85 oC

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Nominal Frequency Total Stability*

FO

CMOS, Dual CMOS

0.1

FO

LVDS/LVPECL/HCSL

0.1

Frequency Stability Grade C

?30

--

212.5 MHz

--

250

MHz

--

+30

ppm

Frequency Stability Grade B

?50

--

+50

ppm

Frequency Stability Grade A

?100

--

+100 ppm

Temperature Stability

Frequency Stability Grade C

?20

--

+20

ppm

Frequency Stability Grade B

?25

--

+25

ppm

Frequency Stability Grade A

?50

--

+50

ppm

Startup Time Disable Time Enable Time

TSU

Minimum VDD until output

--

--

10

ms

frequency (FO) within specification

TD

FO 10 MHz

--

--

5

?s

FO < 10 MHz

--

--

40

?s

TE

FO 10 MHz

--

--

20

?s

FO < 10 MHz

--

--

60

?s

*Note: Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and vibration (not under operation), and 10 years aging at 40 oC.

4

Skyworks Solutions, Inc. ? Phone [781] 376-3000 ? Fax [781] 376-3100 ? sales@ ?

Rev. 1.4 ? Skyworks Proprietary Information ? Products and Product Information are Subject to Change Without Notice ? October 29, 2021

Si510/511

Table 3. Output Clock Levels and Symmetry

VDD = 1.8 V ?5%, 2.5 or 3.3 V ?10%, TA = ?40 to +85 oC

Parameter

Symbol

Test Condition

Min

CMOS Output Logic

VOH

High

0.85 x VDD

CMOS Output Logic

VOL

--

Low

CMOS Output Logic

IOH

3.3 V

?8

High Drive

2.5 V

?6

1.8 V

?4

CMOS Output Logic

IOL

3.3 V

8

Low Drive

2.5 V

6

1.8 V

4

CMOS Output Rise/Fall Time (20 to 80% VDD)

TR/TF

LVPECL Output Rise/Fall Time (20 to 80% VDD)

TR/TF

0.1 to 212.5 MHz, CL = 15 pF

0.1 to 212.5 MHz, CL = no load

0.45 0.3 100

HCSL Output Rise/Fall TR/TF

100

Time (20 to 80% VDD)

LVDS Output Rise/Fall TR/TF

350

Time (20 to 80% VDD)

LVPECL Output

VOC

50 to VDD ? 2 V,

--

Common Mode

single-ended

LVPECL Output Swing VO

50 to VDD ? 2 V, single-ended

0.55

LVDS Output Common Mode

LVDS Output Swing

VOC

100 line-line

VDD = 3.3/2.5 V

100 line-line, VDD = 1.8 V

VO Single-ended, 100 differential termination

1.13

0.83 0.25

HCSL Output Common VOC

50 to ground

0.35

Mode

HCSL Output Swing

VO

Single-ended

0.58

Duty Cycle

DC

All formats

48

Typ --

--

-- -- -- -- -- -- 0.8

0.6

--

--

--

VDD ? 1.4 V 0.8

1.23

0.92 0.35

0.38

0.73 50

Max

Unit

--

V

0.15 x VDD V

--

mA

--

mA

--

mA

--

mA

--

mA

--

mA

1.2

ns

0.9

ns

565

ps

470

ps

800

ps

--

V

0.90 1.33

VPPSE V

1.00 0.45

0.42

V VPPSE

V

0.85 52

VPPSE %

Skyworks Solutions, Inc. ? Phone [781] 376-3000 ? Fax [781] 376-3100 ? sales@ ?

5

Rev. 1.4 ? Skyworks Proprietary Information ? Products and Product Information are Subject to Change Without Notice ? October 29, 2021

Si510/511

Table 4. Output Clock Jitter and Phase Noise (LVPECL)

VDD = 2.5 or 3.3 V ?10%, TA = ?40 to +85 oC; Output Format = LVPECL

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Period Jitter (RMS)

Period Jitter (Pk-Pk)

JPRMS JPPKPK

10k samples1 10k samples1

--

--

1.3

ps

--

--

11

ps

Phase Jitter (RMS)

J

1.875 MHz to 20 MHz integration

--

0.31

0.5

ps

bandwidth2 (brickwall)

12 kHz to 20 MHz integration band-

--

0.8

1.0

ps

width2 (brickwall)

Phase Noise,

N

156.25 MHz

100 Hz 1 kHz

--

?86

--

dBc/Hz

--

?109

--

dBc/Hz

10 kHz

--

?116

--

dBc/Hz

100 kHz

--

?123

--

dBc/Hz

1 MHz

--

?136

--

dBc/Hz

Additive RMS

Jitter Due to

External Power Supply Noise3

JPSR

10 kHz sinusoidal noise 100 kHz sinusoidal noise 500 kHz sinusoidal noise

--

3.0

--

ps

--

3.5

--

ps

--

3.5

--

ps

1 MHz sinusoidal noise

--

3.5

--

ps

Spurious

SPR

LVPECL output, 156.25 MHz, offset>10 kHz

--

?75

--

dBc

Notes: 1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 MHz. 2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz. 3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).

6

Skyworks Solutions, Inc. ? Phone [781] 376-3000 ? Fax [781] 376-3100 ? sales@ ?

Rev. 1.4 ? Skyworks Proprietary Information ? Products and Product Information are Subject to Change Without Notice ? October 29, 2021

Si510/511

Table 5. Output Clock Jitter and Phase Noise (LVDS)

VDD = 1.8 V ?5%, 2.5 or 3.3 V ?10%, TA = ?40 to +85 oC; Output Format = LVDS

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Period Jitter (RMS)

Period Jitter (Pk-Pk)

JPRMS JPPKPK

10k samples1 10k samples1

--

--

2.1

ps

--

--

18

ps

Phase Jitter (RMS)

J

1.875 MHz to 20 MHz integration

--

0.25

0.55

ps

bandwidth2 (brickwall)

12 kHz to 20 MHz integration band-

--

0.8

1.0

ps

width2 (brickwall)

Phase Noise,

N

156.25 MHz

100 Hz 1 kHz

--

?86

--

dBc/Hz

--

?109

--

dBc/Hz

10 kHz

--

?116

--

dBc/Hz

100 kHz

--

?123

--

dBc/Hz

1 MHz

--

?136

--

dBc/Hz

Spurious

SPR

LVPECL output, 156.25 MHz, offset>10 kHz

--

?75

--

dBc

Notes: 1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 MHz. 2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.

Skyworks Solutions, Inc. ? Phone [781] 376-3000 ? Fax [781] 376-3100 ? sales@ ?

7

Rev. 1.4 ? Skyworks Proprietary Information ? Products and Product Information are Subject to Change Without Notice ? October 29, 2021

Si510/511

Table 6. Output Clock Jitter and Phase Noise (HCSL)

VDD = 1.8 V ?5%, 2.5 or 3.3 V ?10%, TA = ?40 to +85 oC; Output Format = HCSL

Parameter

Symbol

Test Condition

Min

Period Jitter

JPRMS

10k samples*

--

(RMS)

Period Jitter

JPPKPK

10k samples*

--

(Pk-Pk)

Phase Jitter (RMS)

J

1.875 MHz to 20 MHz integration

--

bandwidth*(brickwall)

12 kHz to 20 MHz integration band-

--

width* (brickwall)

Phase Noise,

N

100 Hz

--

156.25 MHz

1 kHz

--

10 kHz

--

100 kHz

--

1 MHz

--

Spurious

SPR

LVPECL output, 156.25 MHz,

--

offset>10 kHz

*Note: Applies to an output frequency of 100 MHz.

Typ --

--

0.25

0.8

?90 ?112 ?120 ?127 ?140 ?75

Max 1.2 11 0.30

Unit ps ps ps

1.0

ps

--

dBc/Hz

--

dBc/Hz

--

dBc/Hz

--

dBc/Hz

--

dBc/Hz

--

dBc

8

Skyworks Solutions, Inc. ? Phone [781] 376-3000 ? Fax [781] 376-3100 ? sales@ ?

Rev. 1.4 ? Skyworks Proprietary Information ? Products and Product Information are Subject to Change Without Notice ? October 29, 2021

 ................
................

In order to avoid copyright disputes, this page is only a partial summary.

Google Online Preview   Download