VHDL CODE FOR MULTIPLEXER WITH DATA FLOW DESIGN
UNIT-3
DESIGN COMBINATIONAL CKT USING ARCHITECTURE MODEL
(a) DATA-FLOW MODEL
(b) BEHAVIOR MODEL
(c) STRUCTURAL MODEL
VHDL CODE FOR MULTIPLEXER WITH DATA FLOW MODEL.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUX_4X1 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
S : in STD_LOGIC_VECTOR(1 down to 0);
Y : out STD_LOGIC
);
end MUX_4X1;
architecture MUX_DATA of MUX_4X1 is
begin
Y Y Y Y Y NULL;
END CASE;
END PROCESS;
end MUX_BEH;
VHDL CODE FOR MULTIPLEXER WITH structural style model
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUX4X1 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
S0 : in STD_logic;
S1 : IN STd_logic;
Y : out STD_LOGIC
);
end MUX4X1;
architecture MUX_STRU of MUX4X1 is
COMPONENT AND3
PORT( L,M,O: IN STD_LOGIC; N: OUT STD_LOGIC);
END COmponent;
COMPONENT OR4
PORT( H,I,J,K: IN STD_LOGIC; H1: OUT STD_LOGIC);
END COmponent;
COMPONENT INV_1
PORT( E: IN STD_LOGIC; F: OUT STD_LOGIC);
END COmponent;
for v0:and3 use entity work.and3(and3);
for v4:or4 use entity work.or4(or4);
for u0:inv_1 use entity work.inv_1(inv_1);
SIGNAL S0BAR,S1BAR,W,X,G,Z: STD_LOGIC;
BEGIN
U0: INV_1 PORT MAP (S0,S0BAR);
U1: INV_1 PORT MAP (S1,S1BAR);
V0: AND3 PORT MAP (A,S1BAR,S0BAR,W);
V1: AND3 PORT MAP (B,S1BAR,S0 ,X);
V2: AND3 PORT MAP (C,S1 ,S0BAR,G);
V3: AND3 PORT MAP (D,S1 ,S0 ,Z);
V4: OR4 PORT MAP ( W,X,G,Z,Y);
end MUX_STRU;
--1-bit comparator using behavioral style.
entity comp is
port ( a: in bit_vector(0 to 1);e: out bit_vector(2 downto 0));
end entity;
architecture comp_beha of comp is
begin
process(a)
variable temp : bit;
begin
case a is
when "00" => e e e e null;
end case;
end process;
end architecture;
--1-bit comparator using structural style model
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity COMP_1 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
E : out STD_LOGIC;
L : out STD_LOGIC;
G : out STD_LOGIC
);
end COMP_1;
architecture COMP_STRU of COMP_1 is
component xnor2
port(l, m: in STD_LOGIC; n: out STD_LOGIC);
end component;
component and2
port(x, y: in STD_LOGIC; z: out STD_LOGIC);
end component;
component inv
port( s: in STD_LOGIC; t: out STD_LOGIC);
end component;
for A1:and2 use entity work.and2(and2);
for X1:xnor2 use entity work.xnor2(xnor2);
for I1:inv use entity work.inv(inv);
signal abar,bbar: STD_LOGIC;
begin
I1: INV PORT MAP( A, ABAR);
I2: INV PORT MAP (B,BBAR);
X1: xnor2 port map ( a, b, e);
A1: and2 port map( abar,b,l);
A2: and2 port map(a,bbar,g);
end COMP_STRU;
--4-bit comparator using data flow model.
use IEEE.STD_LOGIC_1164.all;
entity \4_bit\ is
port(
a : in STD_LOGIC_VECTOR(0 to 3);
b : in STD_LOGIC_VECTOR(0 to 3);
agtb : out STD_LOGIC;
aeqb : out STD_LOGIC;
altb : out STD_LOGIC
);
end \4_bit\;
architecture \4_bit_data\ of \4_bit\ is
begin
aeqb ................
................
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