AN0948.2: EFR32 Series 2 Power Configurations and DC-DC

AN0948.2: EFM32 and EFR32 Series 2 DCto-DC Converter

This application note provides an overview of the integrated DCto-DC converter (DC-DC) on EFM32 and EFR32 Series 2 devices. Hardware configuration and software initialization are discussed along with external component recommendations and PCB layout guidance.

EFM32 Series 2 devices with the DC-DC include: ? EFM32PG22 ? EFM32PG23

Wireless EFR32 Series 2 devices with the DC-DC include: ? EFR32BG22 ? EFR32FG22 ? EFR32MG22 ? EFR32FG23 ? EFR32ZG23 ? EFR32BG24 ? EFR32MG24

KEY POINTS

? A DC-to-DC converter can improve overall system energy efficiency.

? EFM32 and EFR32 Series 2 devices integrate a DC-to-DC converter with flexible configuration options.

? Emlib functions fully support the DC-to-DC converter and provide the optimal configuration for the majority of use cases.

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AN0948.2: EFM32 and EFR32 Series 2 DC-to-DC Converter

DC-to-DC Buck Converter Theory

1. DC-to-DC Buck Converter Theory

A DC-to-DC buck converter is a type of switching regulator that efficiently converts a high input voltage to a lower output voltage. A DCto-DC converter is generally much more efficient than a low-dropout (LDO) regulator. For an LDO regulator, the input current generally equals the output current. As the difference between the input voltage and output voltage increases, the power efficiency decreases as more power is dissipated as heat. For a DC-to-DC converter, power output is proportional to power input based on an efficiency rating determined by the load current and switching losses. A DC-to-DC converter's efficiency may typically reach 90% under normal operating conditions, whereas LDO regulator peak efficiency is directly proportional to the output voltage over the input voltage (i.e., if the input is 3.3 V and the output is 1.8 V, then the LDO efficiency is approximately 1.8 V/3.3 V or 54%).

A basic block diagram of a generic DC-to-DC buck converter is shown below:

VDD

Main + Supply ?

VSW PFET NFET

IIND VDCDC

L

ILOAD

C

Figure 1.1. Basic DC-to-DC Buck Converter Block Diagram

DC-to-DC converters typically use one of two modulation schemes: PWM (pulse width modulation) or PFM (pulse frequency modulation). A PWM DC-to-DC converter modulates the on-time of the PFET switch with a constant switching frequency. This method concentrates the noise from the DC-to-DC converter into a single, filterable band. However, due to its constant frequency, the number of switching operations remains the same regardless of the load, and the switching current loss remains constant. A PFM DC-to-DC converter modulates the switching frequency, with increased switching frequency for heavy load currents and decreased switching frequency for light load currents. Due to the variable number of switching operations, the PFM method ensures high efficiency even under light load operation, as less switching results in less switching loss. Though this method is often more efficient, one drawback is that it spreads out the noise spectrum, making it more challenging to filter.

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AN0948.2: EFM32 and EFR32 Series 2 DC-to-DC Converter

DC-to-DC Converter Module Overview

2. DC-to-DC Converter Module Overview

The EFM32 and EFR32 Series 2 devices feature a DC-to-DC buck converter (DC-DC) which requires a single external inductor and a single external capacitor. The input supply is the VREGVDD pin, and the DC-DC produces a nominal 1.8 V output at the VDCDC node to power radio and MCU functions. The DC-DC is an efficient pulse frequency modulation architecture, delivering up to 120 mA of current (see the device datasheet for specific limits). In addition, the DC-DC supports an unregulated bypass mode in which the input voltage is directly shorted to the DC-to-DC output. An integrated programmable supply monitor and dedicated interrupt allows software to enable the bypass switch when the VREGVDD supply voltage is below the minimum allowable voltage for the output current load.

The input supply VREGVDD has a maximum range between 1.8 and 3.8 V but is limited by application parameters, including transient current load, operating junction temperature, and the lifetime average current load.

Refer to the device datasheet for more details on the input supply voltage range.

2.1 PFM Buck Converter

The pulse frequency modulation (PFM) DC-to-DC design in EFM32 and EFR32 Series 2 devices features an entirely new architecture relative to the DC-to-DC converter on EFM32 and EFR32 Series 1 devices. This new design utilizes a fixed peak-current, comparatorbased feedback regulation method. The PFM switching cycle consists of three phases with two periods in which the DC-to-DC converter's PFET and NFET switches are turned on in a complimentary fashion and a third period in which both the PFET and NFET switches are turned off to ensure that the current to the load remains positive or zero.

Figure 2.1. DC-DC Converter Switch Voltage and Inductor Current during switching cycle

A switching cycle is initiated when the DC-DC voltage comparator detects that the output voltage is less than the reference voltage. The PFET switch is closed and begins to conduct, charging the inductor until it reaches the fixed IPK current limit. When the peak current detector triggers, the PFET is switched off, and the NFET is switched on, which discharges the inductor current to zero. When the zerocrossing detector triggers, it turns off the NFET, and the cycle repeats again, waiting for the voltage comparator trigger.

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AN0948.2: EFM32 and EFR32 Series 2 DC-to-DC Converter

DC-to-DC Converter Module Overview

2.2 Bypass Mode and VREGVDD Comparator

In bypass mode, the VREGVDD input voltage is directly shorted to the DC-DC output through an internal switch. Bypass mode is enabled automatically during a power-on-reset. Bypass mode can also be enabled and disabled through software, using the DCDC_CTRL_MODE field. When set to BYPASS, the bypass switch is enabled and DC-to-DC regulation is disabled. Consult the datasheet for the bypass switch impedance specification.

The DC-DC includes a supply comparator circuit to help software determine when the VREGVDD supply is high enough to enable DCto-DC regulation or when to change to bypass mode. Before enabling the DC-DC, the supply comparator must be configured and enabled. The THRESSEL field in the EMU_VREGVDDCMPCTRL register sets the comparator threshold between 2.0 and 2.3 V, and the VREGINCMPEN bit enables the supply comparator. When the comparator is used, DCDC_STATUS_VREGIN can be read by software to determine whether VREGVDD is above or below the established threshold. When this bit is high, indicating that VREGIN is below threshold, the DC-DC should not be enabled and software should wait until the comparator indicates that VREGIN is above threshold.

The VREGVDD comparator can also generate interrupt requests when the input supply is above or below the specified threshold. The VREGINHIGH and VREGINLOW bits in the DCDC_IEN register enable the above and below threshold interrupt requests, respectively. The VREGVDD comparator is active and can request interrupts in EM0 and EM1 only.

Upon any reset event, the status of VREGVDD comparator status is always captured and stored in the VREGIN bit of the EMU_RSTCAUSE register, even if the reset is not caused by VREGVDD being too low. At startup, software should determine if a low VREGVDD condition caused the last reset using logic similar to this:

if (RMU_ResetCauseGet() == (EMU_RSTCAUSE_VREGIN & (EMU_RSTCAUSE_DVDDBOD | EMU_RSTCAUSE_DVDDLEBOD))) handleBrownOutDetectionReset();

else initializeNormally();

If the reset condition above is true, software should keep the device in bypass mode with the DC-DC disabled.

2.3 DC-DC Startup

Out of power-on-reset (POR), the bypass switch is enabled, and the DC-to-DC converter is disabled. Before enabling the DC-DC, software should first configure and enable the VREGVDD comparator. Once the thresholds for the VREGVDD comparator have been configured and the comparator enabled, the VREGIN bit of the DCDC_STATUS register should be checked to ensure that the input supply is above the threshold, at which point the DC-DC can be configured and enabled. The following steps outline this procedure:

1. Set the VREGVDD comparator threshold in EMU_VREGVDDCMPCTRL. 2. Enable the VREGVDD comparator by setting the VREGINCMPEN bit in the EMU_VREGVDDCMPCTRL register. 3. Check the VREGVDD threshold comparator status by reading the VREGIN bit in the DCDC_STATUS register:

? If low, VREGIN is above the programmed threshold, and it is safe to enable the DC-to-DC converter. ? If high, VREGIN is below the programmed threshold and software should leave the bypass switch enabled (MODE = 0 in the

DCDC_CTRL register). 4. For EFM32PG22 and EFR32xG22, enable the DC-DC module by writing 1 to the EN bit in the DCDC_EN register. Note

EFR32xG23, and EFR32xG24 do not have the DCDC_EN register 5. Configure the IPKVAL and DRVSPEED settings in the DCDC_EM01CTRL0 and the DCDC_EM23CTRL0 registers. 6. Enable any required interrupts via the DCDC_IEN register. 7. Enable the DC-to-DC converter by writing 1 to the MODE bit in the DCDC_CTRL register.

When enabled, the DC-DC enters a warmup phase for approximately 100 ?s, then disables the bypass switch and begins using the DC-to-DC core to regulate the output voltage. The RUNNING bit in the DCDC_IF register indicates when the switch from bypass mode to DC-to-DC regulation is complete, however this does not yet indicate that the output is regulated. Until the output load capacitor discharges due to normal current draw from the system, the voltage may be higher than 1.8 V. The REGULATION bit in the DCDC_IF register indicates when the DC-to-DC converter has reached regulation and is providing the desired output voltage.

If the VREGINLOW interrupt occurs, software should immediately return to bypass mode by writing 0 to the MODE bit in the DCDC_CTRL register.

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AN0948.2: EFM32 and EFR32 Series 2 DC-to-DC Converter

DC-to-DC Converter Module Overview

2.4 Recommended Configuration Settings

Certain DC-DC parameters can be adjusted to fine-tune performance, but the majority of applications do not need to use anything other than the recommended settings. All datasheet parameters are specified using the recommended settings detailed in this section. These settings must be in place before the DC-DC is enabled and must not be changed while the DC-DC is active.

The DCDC_EM01CTRL0 and DCDC_EM23CTRL0 registers each have an IPKVAL field to adjust the peak/maximum load current and a DRVSPEED field to adjust the driver speed. DCDC_EM01CTRL0 configures these parameters for operation in EM0 and EM1 while the DCDC_EM23CTRL0 settings apply to EM2 and EM3. The IPKTMAXCTRL field in the DCDC_CTRL register sets the timeout interval for peak current detection, which impacts the voltage ripple at the DC-DC output. The recommended settings are shown in Table 2.1 DRVSPEED, IPKVAL, and IPKMAXCTRL Recommended Settings on page 5.

Table 2.1. DRVSPEED, IPKVAL, and IPKMAXCTRL Recommended Settings

Bit Field EM01CTRL0_IPKVAL EM01CTRL0_DRVSPEED EM23CTRL0_IPKVAL

EM23CTRL0_DRVSPEED DCDC_CTRL_IPKTMAXCTRL

Recommended Setting

9 (LOAD60MA)

1 (DEFAULT_SETTING)

3 (LOAD5MA for EFM32PG22 and EFR32xG22; LOAD36MA for EFR32xG23, and EFR32xG24)

3 (BEST_EFFICIENCY)

4 for EFM32PG22 and EFR32xG22; 16 for EFR32xG23, and EFR32xG24 (TMAX_1P19US)

On supported devices, the DCMONLYEN bit in the DCDC_CTRL register selects between DCM and CCM mode. The default setting (DCMONLYEN = 1) is to use DCM mode, and should not be changed for most applications.

2.5 EM4 Entry

The DC-DC is available in all energy modes except EM4. To enter EM4, the DC-DC must be switched to bypass mode. The system will not enter EM4 if the DC-DC is active; any attempt to do so will be blocked, and the EM4ERR bit in the DCDC_IF register will be set.

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