The 3D-SOI integrated circuit technology developed by MIT ...



Implanted Neural Devices in 3D-SOI Technology

Xiao Yun, Donghwi Kim, Ram Gandhi and Milutin Stanacevic

Department of Electrical and Comp. Engineering, Stony Brook University, Stony Brook, NY, 11794

The 3D-SOI integrated circuit technology offers many advantages over bulk CMOS, including full dielectric device isolation, reduced parasitic junction capacitances, and improved subthreshold slope. It also allows circuit structures that form on several silicon-on-insulator (SOI) substrates to be integrated into a three-dimensional way so that provides higher packing density.

Implantable neural prosthesis and brain machine interfaces require integration of power harvesting, telemetry, low-noise sensing, amplification and analog-to-digital conversion under severe constraints on size and power. The 3D-SOI process offers considerable advantages in realizing this complex systems by reducing interference and providing dense interconnections. Moreover, reduced parasitic capacitance and leakage current, higher noise immunity from on-chip digital circuitry enable designs in SOI technology with lower power consumption, smaller area and better noise efficiency. Comparing to the conventional bulk CMOS technology, the 3D-SOI process avoids many serious drawbacks when the transistor feature size and power supply are scaled down. Additionally, 3D-SOI provides attractive features for designing RF fronted and power recovery circuits. The back metal layer is RF-optimized, which includes metal thicknesses optimized for design of RF passives and tungsten gates shunts for reduced gate series resistance. The devices in one of the tiers have a lower drop over voltage; hence enable us to have better efficiency in the power recovery circuit. The on-chip passives won't create a problem for area since the three-dimensional integration.

We will present implementation of a system containing neural recording, current measuring and power harvesting circuits in a single integrated 3D package.

Stringent constraints are imposed on the design of neural amplifiers. We have designed a neural amplifier in 3D-SOI process. The circuit achieves lower power consumption, smaller area and better noise efficiency factor compared to the standard bulk processes. A symmetric pseudo resistor was realized with resistances on the order of 1015 (, enabling a low cut-off frequency of 0.6 mHz. The simulated performance demonstrates a noise level of 3.07 (V at power consumption level of 6 (W and an area of 0.004mm2.

A current-measuring sensor for electrochemical detection of electroactive neurotransmitters like dopamine and nitric-oxide is implemented. The designed ADC architecture is first-order single bit delta-sigma modulator with programmable oversampling ratio. The potentiostat has a wide dynamic range of currents that span through six orders of magnitude and sensitivity of 1 pA. The current range is digitally by modulating the feedback duty-ratio cycle. The potentiostat can be used to acquire real-time multichannel data from microfabricated neurotransmitter sensor arrays.

The RF Stage consisted of a tuned circuit, wherein the antenna was implanted on chip using the RF-Metal layer. The antenna used up an area of 1mm by 1mm. This was not costly for us due to the magic of 3-D integration, where we would have other circuits below this layer. We have also given facility for conventional antenna of chip for testing purposes.

The Power recovery stage consists of a rectifier, filter and regulator along with circuits for generating required voltage references. These modules where also designed in the C layer (topmost) because of the advantage of the low drop over voltage. These modules worked successfully in simulations and where able to generate required Vdd and Gnd rail voltages.

We have designed a low-power low-noise neural amplifier and a current measuring analog-to-digital converter for recording of neuro potentials and neurochemical signals. The RF fronted and the power recovery sections of the system are also implemented under this process. They demonstrate better power and noise performance over their bulk counterparts. The area of individual circuits is also reduced significantly, since we can have smaller capacitors due to the reduced parasitic capacitance.

In summary, the 3D-SOI process offers considerable advantages for the implementation of fully implantable chip with integrated power harvesting and telemetry, multiple channels of neuro potential and neuro chemical measurements.

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