Department of Electrical and Computer Engineering,



Department of Electrical and Computer Engineering,

University of Calgary

FINAL EXAM FOR ENEL515

APRIL 17th 2001 3 HOURS

NAME:- ID#:-

PLEASE WRITE CLEARLY. USE AN HB GRADE OR SOFTER (DARKER) PENCIL!

WHAT I CAN=T READ WILL MARKED WRONG.

CLOSED BOOK EXAM

SPECIFIC ENEL515 CAUTIONS

DO NOT BRING ANY UNAUTHORIZED MATERIAL INTO THE EXAM ROOM

• You have been provided with an updated SHARC reference sheet, M68000 reference sheet and a comparative programming sheet. You were given the opportunity, prior to the exam, to become aware of the contents of those sheets will be useful to you during the exam. In this quiz you may comparing the characteristics of the 16 bit Motorola 68K CISC processor, the 32 bit AMD 29050 RISC processor, 32/48 bit Analog Devices 21061 DSP processor and other CISC, RISC and DSP processors discussed during this course. Make sure that when you are answering a question you do so in the context of the appropriate processor.

• Many of the concepts in this course are subjective – meaning that there may be more than one valid answer. Make sure that you support your answer.

• If the question says – which is better 29K, 68K or 21K in this situation, then answering 21K will give you no marks, even if true. Support why that answer is true, preferably with examples in point form

NO CALCULATORS ARE ALLOWED IN THIS EXAM

Attempt all THREE questions from SECTION A

and ANY TWO questions from SECTION B.

All questions are approximated weighted equally in terms of marks, but not difficulty

Indicate your estimate of your performance in the table on the attached sheet.

There is a maximum bonus of 5 marks for accurately estimating your marks.

A hint of the time to spend on each part of a question is given by the relative number of marks associated with that question part. Answer the questions in the space provided on the exam sheet. The space and marks allocated are an indication of the depth of the answer expected. Make sure that you provide appropriate documentation of code and answers as marks are allocated for this documentation. Follow standard AC/C++@ conventions and recommended safe practices in your coding.

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SECTION A – ATTEMPT ALL QUESTIONS – Q1 to Q3

Q1 The following code sequence is essentially what was presented by one student for the parallel code associated with cosine synchronous demodulation (Pre-laboratory 3).

| ASSUME that non-volatile registers have been saved as needed and that the DAG registers I4, M4, B4, L4, I3, M3, I12, M12 have been set correctly |

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|1) |F9 = F9 – F9, |R2 = 256; | |

|2) | |F1=dm(I4, M4), |F5=pm(I12, M12); |

|3) lcntr = R2, (do pc, END_DEMOD –1) |

|4) F13=F1*F5, |F9 = F9 + F13, |F1=dm(I4, M4), |F5=pm(I12, M12); |

|5) END_DEMOD: | | | |

|F13=F1*F5, |F9 = F9 + F13; | | |

|6) | |dm(I3, M3) = F9; | |

A) Circle, and label with an A, the COMPUTE component of ONE of the 21k instructions in the table.

1 mark

B) Circle, and label with a B, the first totally parallel instruction in the code 1 mark

C) Circle, and label with a C, the instruction(s) that demonstrates the concept of Filling the algorithm pipeline 1 mark

D) Briefly explain, USING THE CONTEXT OF THIS CODE, the concept of pipelines in parallel instruction processors. I would claim that there are two, probably more pipelines involved in this code. 3 marks

E) The code would have been more understandable if the first instruction had been written as

F9 = 0, R2 = 256;

but that wasn’t not possible. Explain. 2 marks

F) The code will not provide the correct synchronous detection result. There are a number of ways of fixing the code. Would changing instruction 2 to F13 = F13 – F13, F1=dm(I4, M4), F5=pm(I12, M12); be one of them? Discuss. Careful – there are several errors in this student’s code, and some of the errors cancel each other out. 2 marks

There are 10 marks available on this page -- You received __________ PAGE 2 OF 16

G) Explain the differences and relative advantages between processors with a von Neumann architecture and processors with an Harvard architecture. A diagram or two would not go a-miss ( 4 marks

H) Using processors discussed in ENEL515 provide examples of processors with a von Neumann architecture and processors with an Harvard architecture. 2 marks

Von-Neumann _____________________________________________________________________

Harvard _________________________________________________________________________

I) A little hint for question 1H. The SHARC 21k does not have a Harvard architecture but a

Super Harvard ARChitecture. What are the advantages of having a super Harvard architecture over the normal type, and under what circumstances will these advantages disappear on the 21k processor? 4 marks

BONUS QUESTION – because deep down I am a nice guy 2 marks

Consider the code on the previous page. Will instruction 6 be cached? If it is, how do you know? If it is not, why isn’t it? Why is this bonus question a hint to Q1I ?

There are 10 marks + 2 BONUS marks available on this page -- You received __________PAGE 3 OF 16

Q2) A) Saturation – arithmetic -- Design, write and document an 21K assembly language code segment that accesses N-points of a floating point array PMarray[] over the PM data bus, TRIPLES each value and sets all results above +25.0 to be equal to +25.0 before storing the result into a floating point array DMarray[ ] over the DM data bus. Use hardware loops. Marks are associated with code speed BUT DO NOT unroll the loop or use super-scalar (parallel) coding techniques.

The sequence 10.0, 5.0, -20.0, 22.0, 30.0 becomes 25.0, 15.0, -60.0, 25.0, 25.0. 10 Marks

.segment/pm seg_pmda;

.var PMarray[256]; // The initial array

.endseg;

.segment/dm seg_dmda;

.var DMarray[512]; // The final array

.var N; // The number of values to be converted

.endseg

There are 10 marks available on this page -- You received __________PAGE 4 OF 16

B) Briefly explain the difference between SISD, SIMD and VLIW processors. VLIW processors might also be called MIMD processors 3 marks

C) When moving code between SISD and SIMD processors, you would need to double the size of the value in the modify register in order to correctly step through the memory. You can double the size of the value in register R2 using R2 = ASHIFT R2 BY +1; Why can’t you double the size of the value in a modify register using M2 = ASHIFT M2 BY +1;? What would you have to do instead? 3 marks

There is no need to put the .segment, .endseg syntax into the answer for this question

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D) The following questions and answers were given on last year’s ENEL515 exam.

First question The ADSP 21K has both a data memory data bus and a program memory data bus. Give an example (line from a single line loop) of an ADSP 21K instruction that DEMONSTRATES THE ADVANTAGE of having two busses.

First answer R1 = R2 + R3, dm(I4, M4) = R6, pm(I12, M12) = R7;

Second question Give an example (line from a single line loop) of an ADSP 21K instruction that DOES NOT REQUIRE THE USE of two busses.

Second answer R1 = R2 + R3, dm(I4, M4) = R6;’

Because, deep down I am a nice, caring professor (who did not want ANYBODY back), I gave every body the marks and passed them. However looking back on the exam, I realize that really I should have failed everybody because the second answer is actually the answer to the first question. The correct answer to the second question is R1 = R2 + R3; Discuss whether my current analysis of the correct/wrong answers is correct 4 marks

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VERY TRICKY BONUS needing deep understanding of the 21k instruction cycle. Explain why the first answer is the correct answer to question 1 “THE FIRST TIME AROUND THE LOOP” 1 mark

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There are 10 marks + 1 BONUS mark available on this page -- You received __________PAGE 5 OF 16

Q3A) List four major characteristics of DSP algorithms and briefly explain how the architecture of a processor affects the speed with which these characteristics are handled? (1.5 marks each) 6 marks

B) In the take-home quiz for Pre-laboratory 4 we discussed implementing a dedicated IIR filter on a 21k DSP processor. Figure Q3A shows the schematic for a simpler IIR filter to be used in a DSP loop. My version of the DSP “forever” loop is provided in pseudo code format below. It may not necessarily by the fastest approach to implementing the code.

For (ever)

Read A/D value from the memory location A2Daddress – the A to D converter is always ready for access

Process the value through the IIR filter

Write the processed value to a D/A at memory location D2Aaddress – The D to A converter is always ready for access.

End for

Compare and contrast the maximum sampling speed that could be obtained using IIR filters if the delays were implemented using dedicated registers to the speed obtained if the delays were handled by circular buffers. Explain whether your answer would change if the number of delays increased from the 2 shown in this code to 5 or greater for a more complex IIR filter being run on the 21k processor. You should not actually have to write out the code in order to compare the processor characteristics. 4 marks

There are 10 marks available on this page -- You received __________ PAGE 6 OF 16

C) Write the 21k assembly code for the dedicated IIR filter shown in Figure 3. Optimize your code for speed without using parallel operation instructions (6 marks). Plan ahead so that you can answer Question 3D A second resource chart is available amongst the figures. Total 6 marks

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B) Identify 4 places where you could save a cycle in your code. For full marks you should provide examples of as many different types of SHARC parallel instructions as possible 4 marks

There are 10 marks available on this page -- You received __________ PAGE 7 OF 16

ATTEMPT ANY TWO QUESTIONS FROM SECTION B (Q4 to Q7)

THE QUESTIONS IN THIS SECTION ARE INTENDED TO BE MORE DIFFICULT

THAN THOSE FROM SECTION A

Q4 A) Consider the A/D converter that is part of Figure 3A, the question on IIR filters. Draw labelled diagrams to show how the A/D converter might be hooked up to the 68332 CISC processor and to the 21k DSP processor. 3 marks

B) This is a reworded question from last year’s exam. Very few people got the correct answer, which is why I set one of the components of Pre-laboratory Quiz 3 and have asked the question again.

Consider the following code sequence which access the A/D and D/A converters associated with the IIR filter in Q3. An Analog to Digital converter can be accessed using memory address A2Daddress, and a Digital to Analog Converter can be accessed using memory address D2Aaddress. One of the code sequences is valid, the other is not. Which is correct, which is incorrect and why? 3 marks

|Code Sequence 1 |Code Sequence 2 |

| | |

|R1 = dm(A2Daddress); |R1 = pm(D2Aaddress); |

|R1 = (R1 + R1) / 2; |R1 = (R1 + R1) / 2; |

C) Compare and contrast the efficiency of implementing FIR and IIR filters on processors with, and on processors without, parallel instruction capabilities. 4 marks

There are 10 marks available on this page -- You received __________ PAGE 8 OF 16

D) DAG register i13 contains the address of the start of an array of integer numbers. Write a 21k assembly language code segment that places the number 1 in the initial element of the array, the number 0 in the next element, the number 1 in the next, the number 0 in the next and so on through the loop. Use a hardware loop construct and code for speed using parallel instructions. 10 marks

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There are 10 marks available on this page -- You received __________ PAGE 9 OF 16

Q5. A) For any processor there are major differences between developing code using a subroutine and developing code using an interrupt service routine. What are these major differences? 3 marks

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One of the advantages of using the 21k processor interrupts in ENEL515 compared to the 68k processor interrupts in ENEL415 is the fact that we can use the interrupts within a “C”-wrapper. This means we can make use of calls to the real-time run-time library functions interrupt( ) and interruptf( )

B) Explain the advantages and disadvantages of interrupts within a “C” wrapper 3 marks

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C) Explain the practical details of interrupts within a “C” wrapper both from the point of view of the programmer developing the real-time, run-time library functions and from the person using the run-time library functions.

HINT – One way of answering this question is to discuss what would be necessary to add, and then use, a real-time, run-time interrupt library to the 68k processor or other processor. 4 marks

There are 10 marks available on this page -- You received __________ PAGE 10 OF 16

D)

• A 12-bit memory-mapped A/D converter is located on the data bus at location A2Daddress.

• The status register for the A/D converter is located at address A2Daddress + 1.

• Each time the A/D converter is ready for access, roughly every 5 or 6 minutes, it causes an interrupt which cause the “C” code compatible ADSP-21K assembly code back-ground, interrupt service routine, void READA2D(void), to be run

• After being called 16 times, the ISR stores the floating point average of the previous 16 A/D values into memory location FLOATANSWER and then deactivates all interrupts.

• Bits 31 and 30 are the INTERRUPT CONTROL BITS of the A/D status register.

• BIT 31 set to 1 indicates that the A/D has caused an interrupt and will continue to cause an interrupt.

• BIT 30 controls whether further interrupts can be activated. It automatically clears each time an interrupt occurs.

• The remaining bits of the status register have other functionality and must remain unchanged.

The mission, if you wish to accept it, is to write the

“C” code compatible ADSP-21K assembly code back-ground, interrupt service routine, void READA2D(void).

The table below shows the values input to the A/D, the value output by the A/D and the value returned by the subroutine. There are marks for assuring that this relationship is true for your code.

|Voltage Input |A/D 12-bit value Output |FLOATANSWER value |

|1.5V |0x018 |1.5 |

|2V |0x020 |2.0 |

|-1V |0xFE0 |-1.0 |

10 marks

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There are 10 marks available on this page -- You received __________ PAGE 11 OF 16

Q6) DSP algorithms typically involve extensive memory operation, multiplications and additions inside a loop. Figure 6A shows the pseudo code of a loop made up of a number of instructions Instruction1, Instruction2 through to InstructionK. One approach to reducing the code speed is to double the loop size but go around half as often as shown in Figure 6B, and then rearrange the instructions as appropriate.

A) Consider that Figure 6A and 6B represent the pseudo code for an integer DSP algorithm running on a Motorola 68332 microprocessor. Explain why you would expect little speed improvement between the code for Figure 6B when compared to the code for Figure 6A 3 marks

B) Consider that Figure 6A and 6B represent the pseudo-code for a DSP algorithm running on an Advanced Micro Devices AMD29k processor. Explain why you would expect little speed improvement between the code for Figure 6B when compared to the code for Figure 6A if this was an integer DSP algorithm but significantly more speed improvement if this was a floating point DSP algorithm. 3 marks

C) Consider that Figure 6A and 6B represent the pseudo-code for a DSP algorithm running on an Analog

Devices ADSP21061X processor. Explain why you would expect speed improvement between the code for Figure 6B when compared to the code for Figure 6A regardless of whether this was a DSP integer algorithm or a floating point DSP algorithm. 4 marks

There are 10 marks available on this page -- You received __________ PAGE 12 OF 16

D) With DSP loops running on 68k CISC and 29k RISC processors you can gain speed by rewriting the code using down-counting loops using pointer operations. Explain these concepts and why they offer speed advantages over other code practices on these processors, and little advantage on the 21k DSP processor 4 marks

E) Another concept associated with the speed improvement of DSP algorithms is to UN-ROLL the loop, rearrange the instructions and then RE-ROLL the loop. Consider the pseudo-code in Figure 6A. Demonstrate and explain how the code might look with a 21k processor after “un-rolling and re-rolling” the loop after rearranging the instructions for additional speed.

2 marks

F) What would you have to do to gain an equivalent speed improvement if the DSP algorithm formed part of an ISR routine and did not involve a loop? For example would be an ISR routine that processed one point through an IIR filter 4 marks

There are 10 marks available on this page -- You received __________ PAGE 13 OF 16

Q7) Don=t you just hate it when

• have done research beyond the course content,

• have heavily reviewed one area you thought the instructor kept on deliberately emphasizing,

and then the examiner does not ask any questions in that area! Here is a chance to overcome that problem.

Make up a question related to this course and correctly answer it. (20 marks)

TO RECEIVE FULL MARKS the question should satisfy the following criteria

1. Be at a difficulty level appropriate for a final exam question in the 4th year of an Electrical and Computer Engineering program. Quick test -- Would it be suitable for next year=s final?

2. It should NOT be equivalent to any exam question already asked in this course.

3. Questions and answers that are a simple regurgitation of a concept handled in class will receive a D grade (around 6 -- 8 marks). Questions and answers that give a new insight into a concept handled in class will receive a C or a B grade (11 – 14 marks). Questions that, under different circumstances, would present A CHALLENGE FOR YOU to answer in either Section A or Section B of a final exam will receive B or A grade (14 and up), if answered correctly. A good mark on this question would be 15 out of 20.

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EXTRA PAGE ---- IN-CASE YOU NEED IT FOR A LONG ANSWER

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Performance Analysis Sheet – Maximum Bonus Marks 5%

FINAL EXAM FOR ENEL515, APRIL 17th 2001

NAME:- ID#:-

Good embedded software developers keep track of their progress and can estimate their success. In the table below, indicate questions attempted and your estimate of how well you have answered the question. For each estimate that matches the mark you actually receive, you will receive a bonus mark to make up for the time lost answering this section. No marks for correctly estimating that you did not answer a question (

-- Maximum bonus 5 marks – 6 bonus marks available

| | |MAXIMUM MARK |YOUR ESTIMATE OF YOUR PERFORMANCE | |

|MARK RANGES ARE A > 15 > B > 13 > C > 11 > D > 8 > F |

| |

|ATTEMPT ALL QUESTIONS FROM SECTION A |

| | | |Circle Your |Give Your | |

| | | |Expected Grade |Expected Mark | |

| | |20 + 2 BONUS | | | |

|SECTION A Q1 | | |A B C D F |/ 20 |Basic general knowledge |

| | | | | |(via Pre-Lab 3) |

| | | | | |Coding and processor comparison |

|SECTION A Q2 | |20 + 1 BONUS |A B C D F |/ 20 | |

| | |20 | | |Programming concepts in DSP algorithms |

|SECTION A Q3 | | |A B C D F |/ 20 | |

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|ATTEMPT ANY TWO QUESTIONS FROM SECTION B – IF YOU ATTEMPT THREE, THE THIRD WILL BE IGNORED |

|SECTION B QUESTIONS ARE INTENDED TO BE SIGNIFICANTLY MORE DIFFICULT THAN SECTION A QUESTIONS |

| | | | | |High speed code development |

|SECTION B Q4 | |20 |A B C D F |/ 20 |in embedded DSP system |

| | |20 | | |Interrupt handling |

|SECTION B Q5 | | |A B C D F |/ 20 | |

| | | | |/ 20 |DSP concepts and optimization |

|SECTION B Q6 | |20 |A B C D F | | |

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|SECTION B Q7 | |20 |A B C D F |/ 20 |Your choice of question and answer |

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|YOUR ESTIMATE OF YOUR FINAL MARK – 103 available |TOTAL / 100 | |

Process management component of the exam

Bonus if prediction of mark on a question is accurate to +-1

(estimates of unanswered questions excluded)

Bonus if prediction of final mark on quiz is accurate to +-3

Maximum of 5 Bonus marks – 6 bonus marks available

EXTRA PAGES 1 OF 6

Essentials of the Motorola 68K processor architecture

[pic]

Essentials of the Analog Devices ADSP-21K processor Architecture

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FIGURE 3A -- Schematic of an IIR filter. The 12-bit dual-sided A to D converter is accessed through memory location A2DLOC and the 12-bit dual-sided D to A converter is accessed through memory location D2ALOC. The A2D and D2A converters are always ready for access.

Memory mapped A/D convertor Memory mapped D/A convertor

Address = A2Daddress Address = D2Aaddress

ADDER

(Also SUBRACTOR

A1 = X0.9 A3 = 0.00255

MULTIPLIER

DELAY UNIT

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EXTRA RESOURCE AVAILABILITY CHART NAME ______________ ID# _________

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Figure 6 Figure 6A shows the pseudo code of a loop made up of a number of assembly language instructions Instruction1, Instruction2 through to InstructionK. One approach to reducing the code speed is to double the loop size but go around half as often as shown in Figure 6B, and then rearrange the instructions as appropriate.

|For (count = 0; count < N; count++) { |For (count = 0; count < N / 2; count++) { |

|Instruction1 |Instruction1 |

|…...Instruction2 |…...Instruction2 |

|….. Instruction3 |….. Instruction3 |

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| |…...Instruction2 |

| |….. Instruction3 |

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|Figure 6A |Figure 6B |

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