Adiabatic Technique For Power Efficient Logic Circuit Design
CHAPTER 1INTRODUCTION1.1 HISTORY"Adiabatic" is a term of Greek origin that has spent most of its history associated with classical?thermodynamics. It refers to a system in which a transition occurs without energy (usually in the form of heat) being either lost to or gained from the system. In the context of electronic systems, rather than heat, electronic charge is preserved. Thus, an ideal adiabatic circuit would operate without the loss or gain of electronic charge.The first usage of the term "adiabatic" in the context of circuitry appears to be traceable back to a paper presented in 1992 at the Second Workshop on Physics and Computation. Although an earlier suggestion of the possibility of?energy recovery?was made by?Charles H. Bennett?where in relation to the energy used to perform computation, he stated "This energy could in principle be saved and reused".1.2 DEFINITIONEtymology of the term "adiabatic logic". Because of the?second law of thermodynamics, it is not possible to completely convert energy into useful work. However, the term "adiabatic logic" is used to describe logic families that could theoretically operate without losses. The term "quasi-adiabatic logic" is used to describe logic that operates with a lower power than static CMOS logic, but which still has some theoretical non-adiabatic losses.PRINCIPLEThere are several important principles that are shared by all of these low-power adiabatic systems. These include only turning switches on when there is no potential difference across them, only turning switches off when no current is flowing through them, and using a power supply that is capable of recovering or recycling energy in the form of electric charge. To achieve this, in general, the power supplies of adiabatic logic circuits have used constant current charging (or an approximation thereto), in contrast to more traditional non-adiabatic systems that have generally used constant voltage charging from a fixed-voltage power supply.1.4 LOGIC CIRCUITVery-large-scale integration?(VLSI) is the process of creating an?integrated circuit?(IC) by combining hundreds of thousands of?transistors?or devices into a single chip. VLSI began in the 1970s when complex?semiconductor?and?communication?technologies were being developed. The?microprocessor?is a VLSI device. Before the introduction of VLSI technology most ICs had a limited set of functions they could perform. An?electronic circuit?might consist of a?CPU,?ROM,?RAM?and other?glue logic. VLSI lets IC designers add all of these?into one chip.CHAPTER 2CONVENTIONAL CMOS LOGIC2.1 INTRODUCTIONComplementary metal-oxide-semiconductor, abbreviated as cmos ,is a technology for constructing integrated circuits. CMOS Technology is used in microprocessor, microcontroller, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensor , data converter , and highly integrated transceivers for many types of communication . In 1963, Frank Wanlass patented CMOS while working for Fairchild semiconductor. CMOS is also sometimes referred to as?complementary-symmetry metal–oxide–semiconductor?(or?COS-MOS).?The words "complementary-symmetry" refer to the typical design style with CMOS using complementary and symmetrical pairs of?p-type?and?n-type?metal oxide semiconductor field effect transistors?(MOSFETs) for logic functions. Two important characteristics of CMOS devices are high?noise immunity?and low static?power consumption.?Since one?transistor?of the pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much?waste heat?as other forms of logic, for example?transistor–transistor logic?(TTL) or?N-type metal-oxide-semiconductor logic (NMOS) logic, which normally have some standing current even when not changing state. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in?very-large-scale integration?(VLSI) chips.The phrase "metal–oxide–semiconductor" is a reference to the physical structure of certain?field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a?semiconductor material.? HYPERLINK "" \o "Aluminium" Aluminium?was once used but now the material is?polysilicon. Other?metal gates?have made a comeback with the advent of?high-κ?dielectric materials in the CMOS process, as announced by IBM and Intel for the?45 nanometer?node and smaller sizes. 2.2 TECHNICAL DETAILS "CMOS" refers to both a particular style of digital circuitry design and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates?less power?than?logic families?with resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes. As of 2010, CPUs with the best?performance per watt?each year have been CMOS?static logic?since 1976. CMOS circuits use a combination of p-type and n-type?metal–oxide–semiconductor field-effect transistor?(MOSFETs) to implement?logic gates?and other digital circuits. Although CMOS logic can be implemented with discrete devices for demonstrations, commercial CMOS products are integrated circuits composed of up to billions of transistors of both types, on a rectangular piece of?silicon?of between 10 and 400?mm2.CMOS always uses all enhancement-mode MOSFETs (in other words, a zero gate-to-source voltage turns the transistor off).2.3 POWER DISSIPATION2.3.1 STATIC DISSIPATIONBoth NMOS and PMOS transistors have a gate–source?threshold voltage, below which the current (called?sub threshold?current) through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd? might have been 5?V, and Vth?for both NMOS and PMOS might have been 700?mV). A special type of the CMOS transistor with near zero?threshold voltage?is the?native transistor.SiO2?is a good insulator, but at very small thickness levels electrons can tunnel across the very thin insulation; the probability drops off exponentially with oxide thickness. Tunnelling current becomes very important for transistors below 130?nm technology with gate oxides of 20?? or thinner.Small reverse leakage currents are formed due to formation of reverse bias between diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations.If the ratios do not match, then there might be different currents of PMOS and NMOS; this may lead to imbalance and thus improper current causes the CMOS to heat up and dissipate power unnecessarily.2.3.2 DYNAMIC DISSIPATION Charging and discharging of load capacitances CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. In one complete cycle of CMOS logic, current flows from VDD?to the load capacitance to charge it and then flows from the charged load capacitance (CL) to ground during discharge. Therefore, in one complete charge/discharge cycle, a total of Q=CLVDD?is thus transferred from VDD?to ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by the average voltage again to get the characteristic switching power dissipated by a CMOS device: P=0.5C.V^2.f?{\displaystyle P=0.5CV^{2}f}.Since most gates do not operate/switch at every?clock cycle, they are often accompanied by a factor?α{\displaystyle \alpha }, called the activity factor. Now, the dynamic power dissipation may be re-written as P=αC.V^2.f?{\displaystyle P=\alpha CV^{2}f}.A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data has an activity factor of 0.1.?If correct load capacitance is estimated on a node together with its activity factor, the dynamic power dissipation at that node can be calculated effectively. Short-circuit power dissipation Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example, from off to on, both the transistors will be on for a small period of time in which current will find a path directly from VDD?to ground, hence creating a?short-circuit current. Short-circuit power dissipation increases with rise and fall time of the transistors.An additional form of power consumption became significant in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. During the middle of these transitions, both the NMOS and PMOS logic networks are partially conductive, and current flows directly from VDD?to VSS. The power thus used is called?crowbar?power. Careful design which avoids weakly driven long skinny wires ameliorates this effect, but crowbar power can be a substantial part of dynamic CMOS power. NMOSNMOS is built on a p-type substrate with n-type source and drain diffused on it. In NMOS, the majority carriers are electrons. When a high voltage is applied to the gate, the NMOS will conduct. Similarly, when a low voltage is applied to the gate, NMOS will not conduct. NMOS are considered to be faster than PMOS, since the carriers in NMOS, which are electrons, travel twice as fast as the holes. PMOSP- channel MOSFET consists P-type Source and Drain diffused on an N-type substrate. Majority carriers are holes. When a high voltage is applied to the gate, the PMOS will not conduct. When a low voltage is applied to the gate, the PMOS will conduct. The PMOS devices are more immune to noise than NMOS devices.2.4 CMOS WORKING PRINCIPLEIn CMOS technology, both N-type and P-type transistors are used to design logic functions. The same signal which turns ON a transistor of one type is used to turn OFF a transistor of the other type. This characteristic allows the design of logic devices using only simple switches, without the need for a pull-up resistor.In CMOS?logic gates?a collection of n-type MOSFETs is arranged in a pull-down network between the output and the low voltage power supply rail (Vss or quite often ground). Instead of the load resistor of NMOS logic gates, CMOS logic gates have a collection of p-type MOSFETs in a pull-up network between the output and the higher-voltage rail (often named Vdd).Thus, if both a p-type and n-type transistor have their gates connected to the same input, the p-type MOSFET will be ON when the n-type MOSFET is OFF, and vice-versa.?CMOS offers relatively high speed, low power dissipation, high noise margins in both states, and will operate over a wide range of source and input voltages (provided the source voltage is fixed).2.5 CMOS INVERTERCMOS circuits are constructed in such a way that all?P-type metal-oxide-semiconductor?(PMOS) transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all?NMOS?transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low?resistance?between its source and drain contacts when a low gate?voltage?is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. INCLUDEPICTURE "" \* MERGEFORMATINET Fig 2.5 CMOS INVERTERCase1: when A=Vi=0, NMOS: VGS=VG-VS =Vi -0 =Vi =0 => OFF PMOS: VGS=VG-VS =Vi -VDD =0- VDD =- VDD =>ONCase2: when A=Vi= VDD, NMOS: VGS=VG-VS =Vi -0 =Vi = VDD => ON PMOS: VGS=VG-VS =Vi -VDD = VDD - VDD =0 =>OFFTRUTH TABLE:INPUTAPMOSNMOSOUTPUTVOUT0ONOFF11OFFON0when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small. The output, therefore, registers a high voltage.On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an ON (low resistance) state, allowing the output from drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a current drawn into Q placing Q above ground is small. This low drop results in the output registering a low voltage.In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this behavior of input and output, the CMOS circuit's output is the inverse of the input.The power supplies for CMOS are called VDD?and VSS, or VCC?and Ground(GND) depending on the manufacturer.2.6 CMOS NANDIn digital electronics, the nand gate is a logic gate which produces an output of low if it’s both inputs are high & high for any other inputs. A NAND gate is negated AND or NOT AND.In CMOS NAND circuit, PMOS are connected in parallel and NMOS is connected in series.If A is low and B is low then, output is high.If A is low and B is high then, output is high.If A is high and B is low then, output is high.If A is high and B is high then, output is low.Case1: when A=0 & B=0, NMOS-1: VGS=VG-VS =A -0 =A =0 => OFF NMOS-2: VGS=VG-VS =B -0 =B =0 => OFF PMOS-1: VGS=VG-VS =A-VDD =0- VDD =- VDD =>ON PMOS-2: VGS=VG-VS =B -VDD =0- VDD =- VDD =>ONCase2:when A=0 & B=VDD, NMOS-1: VGS=VG-VS =A -0 =A =0 => OFF NMOS-2: VGS=VG-VS =B -0 =B = VDD => ON PMOS-1: VGS=VG-VS =A-VDD =0- VDD =- VDD =>ON PMOS-2: VGS=VG-VS =B -VDD = VDD - VDD =0 =>OFF Fig: 2.6 CMOS NANDTRUTH TABLE:INPUT AINPUT BPMOS 1PMOS2NMOS1NMOS2OUTPUTVout00ONONOFFOFF101ONOFFOFFON110OFFONONOFF111OFFOFFON ON02.7 CMOS NORIn digital electronics, the nor gate is a logic gate which produces an output of high if its both inputs are low & low for any other inputs. A NOR gate is negated OR or NOT OR.In CMOS NOR circuit, PMOS are connected in serirs and NMOS is connected in parallel.If A is low and B is low then, output is high.If A is low and B is high then, output is low.If A is high and B is low then , output is low.If A is high and B is high then, output is low.2.7.1 OPERATIONCase1:when A=0 & B=0, NMOS-1: VGS=VG-VS =A -0 =A =0 => OFF NMOS-2: VGS=VG-VS =B -0 =B =0 => OFF PMOS-1: VGS=VG-VS =A-VDD =0- VDD =- VDD =>ON PMOS-2: VGS=VG-VS =B -VDD =0- VDD =- VDD =>ONCase2:when A=0 & B=VDD, NMOS-1: VGS=VG-VS =A -0 =A =0 => OFF NMOS-2: VGS=VG-VS =B -0 =B = VDD => ON PMOS-1: VGS=VG-VS =A-VDD =0- VDD =- VDD =>ON PMOS-2: VGS=VG-VS =B -VDD = VDD - VDD =0 =>OFF Fig: 2.7 CMOS NORTRUTH TABLE:INPUT AINPUT BPMOS 1PMOS2NMOS1NMOS2OUTPUTVout00ONONOFFOFF101ONOFFOFFON010OFFONONOFF011OFFOFFON ON0CHAPTER 3ECRL (Efficient Charge Recovery Logic)Both share the property, that they are operated with a four-phase power-clock. ECRL, based on the Cascade Voltage Switch Logic (CVSL), uses a cross-coupled PMOS pair as latching element. Logic blocks constructed of NMOS transistors only are used for PFAL and ECRL. As families use identical function blocks, design procedures presented for CVSL [28] can be used for ECRL. Logic blocks are connected from the power-clock and from the output to GND for ECRL.3.1 FOUR-PHASE POWER-CLOCKAdiabatic Logic circuits are operated with an oscillating power-supply, the so-called power-clock. Depending on the regarded adiabatic family, more than one power clock signal is used to operate an system consisting of Adiabatic Logic gates. In this work adiabatic families are employed, that use a four-phase power-clock φ0-φ3. Each power-clock cycle consists of four intervals. In the evaluate (E) interval, the outputs are evaluated from the stable input signals. During the hold (H) interval, outputs are kept stable for supplying the subsequent gate with a stable input signal. Energy is recovered in the interval called recover (R). And for symmetry reasons a wait (W) interval is inserted, as symmetric signals are easier and more efficient to be generated. Data in adiabatic systems is processed in a pipeline fashion, data is handed over as shown in Fig. 3.1. Valid data words 1, 2, 3 and 4 are sketched in phase φ0. Data word 1 is transferred during the H interval of φ0 and while φ1 is in E..Fig: 3.1 Scheme of the four-phase power-clockIt is processed by the logical function given in the succeeding gate and valid at the outputs as 1? for further processing in the next gates. As mentioned before, signals have to be kept constant during E, therefore a 90° phase shift between subsequent phases is obtained. In a pipeline, subsequent gates have to be connected to the right phases in order to guarantee a transfer of valid input data.3.2 Loss Mechanisms in Adiabatic LogicIn an ideal adiabatic system loss are expected to follow, but shrinking devices into the sub-μm regime and the non-existence of zero-Vth transistors lead to additional loss mechanisms. These effects can dominate the energy consumption and also exhibit a lower bound for the energy dissipation. With ongoing shrinking, leakage currents gain more impact on the overall dissipation of static CMOS gates. One of the dominant leakage currents is the so-called sub-threshold current. It is expressed by where VT is the thermal voltage, Vth is the threshold voltage of the device and VGS and VDS are the terminal voltages. As long as VDS is zero, no leakage current will flow. Only for values of VDS that are multiples of the thermal voltage, the leakage increases to its maximum value. Besides that, also a junction leakage exists and in state-of-the-art CMOS processes leakage currents tunnel through the thin gate oxide. In Adiabatic Logic, during evaluation, hold and recovery, leakage currents flow from the voltage supply to ground, leading to dissipation of charge that cannot be recovered. All leakage mechanism can be summarized in a mean current Ileak, that leads to the energy consumption per cycle ofsFig: 3.2 EAL are proportional, leakage losses Eleak are inverse proportional to the frequency and the non-adiabatic losses are independent of the frequency. An optimum frequency exists for Adiabatic Logic circuits, as can be seen from the overall loses∑Leakage-related dissipation increases for lower frequencies, as leakage losses are accumulated over a longer time interval. Discharging a gate in ECRL will lead to a residual voltage at the output node that is in the range of the threshold voltage Vth,p of the PMOS device. As long as the gate evaluates the same input in the next cycle, in ECRL, the residual charge will be reused in the next cycle, otherwise it is dismissed to ground. Besides that, in ECRL the output cannot instantly follow the rising power-clock. Only when the power-clock is at least |Vth,p|, the charging path over the PMOS device is opened. Then the output voltage follows the power-clock abruptly, leading to a dynamic loss. All these losses are related to the threshold voltage and lead to a non-adiabatic dissipation ofNon-adiabatic losses are independent of the operating frequency, leading to an offset in the energy dissipation over the whole frequency range. Thus, three loss mechanisms that contribute to the overall losses are found in Adiabatic Logic. Adiabatic losses are dependent on the operating frequency f . Figure 3.2 shows the three loss mechanisms in dependence of the frequency, and the overall dissipation is gained by summarizing all three components. A minimum dissipation of the energy at a certain frequency is observed. Therefore an optimum frequency exists in Adiabatic Logic, where energy consumed per cycle is minimized.3.3 ECRL Basic gates3.3.1 ECRL Inverter:In ECRL inverter, two inverter are cross- coupled to each other and one inverter’s input is other’s output and vice versa. The ECRL inverter works same as that of basic operation of ECRLFig: 3.3.1 ECRL INVERTER3.3.1.1 OPERATIONCASE1:IF in=0; in--=1;Then out--=1; out=0;CASE2:IF in=1; in--=0;Then out--=0; out=1;3.3.2 ECRL NANDIt functions same as that of CMOS NAND circuitA NAND gate (Negated AND or NOT AND) is a logic gate which produces an output that is false only if all its inputs are true. A LOW (0) output results only if both the inputs to the gate are HIGH (1); if one or both inputs are LOW(0), a HIGH (1) output results. The NAND gate is significant because any Boolean function can be implemented by using a combination of NAND gates. This property is called functional completeness.sFig: 3.3.2 ECRL NAND3.3.3 ECRL NOR:ECRL NOR circuit functions same as that of CMOS NOR circuit.The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a LOW output (0) results.NOR is the result of the negation of the OR operator.Fig: 3.3.3 ECRL NORCHAPTER 4POWER COMPARISON4.1 Voltage Scaling—A Comparison of Static CMOS and Adiabatic LogicAn easy and powerful way to reduce losses in static CMOS is by reducing the voltage supply VDD .Quadratic dependence of the energy dissipation on VDD due to dynamic losses:The limiting factor for voltage scaling is the propagation delay tp, that is increased while the voltage is decreasedwhere tτ is the input slope, α _ is the velocity saturation parameter, and ID0 is the drain current for VGS = VGD = VDS. ongoing miniaturization [34], therefore the first term of above equation can be neglected for state-of-the-art CMOS technologies. Using ID ∝ (VGS ?Vth) in saturation the dependence of the delay on the voltage supply is found: A trade-off exists between speed and power consumption, therefore the voltage can only be reduced to a level where no timing constraints in the design are violated. The critical path in a static CMOS design determines the maximum degree to which the voltage can be reduced. In designs where only a few critical paths exist, but many paths have a positive slack after reducing the supply voltage, the gain from globallyreducing the supply voltage is not satisfying. To make voltage scaling more effective one can try to break up the critical paths to allow further reduction of voltage and thus power, and also using different voltage domains for fast and slow paths could increase the benefits of scaling . Delay is not a concern for Adiabatic Logic circuits, as the maximum possible frequency is far above the optimum frequency for an energy-efficient operation of gates and systems. Looking into the frequency regime where adiabatic losses dominate the energy consumption of Adiabatic Logic, it is expected that the reduction of the supply voltage will lead to a benefit in energy consumption. On first sight a dependence of V 2 DD is observed, but the on-resistance of the transistor in the charging path is also a function of the supply voltage. If the overdrive voltage VGS ? Vth is reduced by reducing the supply voltage, the resistance is increased. As long as VDD is far above Vth, the dissipated energy isThus, Adiabatic Logic also gains from voltage scaling, but the ESF on gate level will decrease if voltage reduction is applied:Leakage losses are also impacted by reducing the supply voltage. As long as the leakage losses are negligible compared to the dynamic losses in static CMOS, and as long as the adiabatic circuit is not operated in the leakage dominated regime, and if non-adiabatic losses are negligible, the impact of voltage scaling on the ESF can be estimated by above equation. The lower bound for VDD in static CMOS is mainly limited by timing constraints, including margins for variations in the process and fluctuations in the temperature and supply voltage. Supply voltage reduction in Adiabatic Logic is not limited by timing constraints. But a functional limit for ECRL and PFAL is observed when reducing VDD. Minimum supply voltages are given byBelow this lower bound, malfunctions of circuits constructed by ECRL gates appear. In ECRL, the NMOS device is responsible to keep one output node at ground potential, and the PMOS device charges the dual output node. Thus in ECRL the voltage supply has to be higher than the highest absolute thresholdvoltage value. In the ECRL gate, the output node has to be at least loaded to Vth,n to make the NMOS device in the latch conductive that is responsible for keeping the dual output node at ground. The input device’s source node is connected to the output node, that is expected to be at least Vth,n. Thus the gate voltage of the input device needs a voltage of greater than 2 · Vth,n to be conducting. Finally the reduction in the voltage levels will degrade the noise margin for static CMOS as well as for Adiabatic Logic. Energy reduction via supply voltage scaling will thus be a trade-off between energy and robustness of the design.4.2 Power Consumption Value:CHAPTER 5APPLICATION (CARRY LOOK AHEAD ADDER)A?carry-lookahead adder?(CLA) or?fast adder?is a type of?adder?used in?digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits. It can be contrasted with the simpler, but usually slower,?ripple-carry adder?(RCA), for which the carry bit is calculated alongside the sum bit, and each bit must wait until the previous carry bit have been calculated to begin calculating its own result and carry bits. The carry-lookahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger-value bits of the adder.5.1 RIPPLE CARRY ADDERMultiple full adder circuits can be cascaded in parallel to add an N-bit number. For an N- bit?parallel?adder, there must be N number of full adder circuits. A ripple carry adder is a logic circuit in which the carry-out of each full adder is the carry in of the succeeding next most significant full adder. It is called a ripple carry adder because each carry bit gets rippled into the next ?stage. In a ripple carry adder the sum and carry out bits of any half adder stage is not valid until the carry in of that stage occurs. Propagation delays inside the logic circuitry is the reason behind this. Propagation delay is time elapsed between the application of an input and occurance of the corresponding output. Consider a NOT gate, When the input is “0” the output will be “1” and vice versa. The time taken for the NOT gate’s output to become “0” after the application of logic “1” to the NOT gate’s input is the propagation delay here. Similarly the carry propagation delay is the time elapsed between the application of the carry in signal and the occurance of the carry out (Cout) signal.?Sum out S0 and carry out Cout of the Full Adder 1 is valid only after the propagation delay of Full Adder 1. In the same way, Sum out S3 of the Full Adder 4 is valid only after the joint propagation delays of Full Adder 1 to Full Adder 4. In simple words, the final result of the ripple carry adder is valid only after the joint propogation delays of all full adder circuits inside it.Full adder is a logic circuit that adds two input operand bits plus a Carry in bit and outputs a Carry out bit and a sum bit.. The Sum out ?(Sout) of a full adder is the XOR of input operand bits A, B and the Carry in (Cin) bit.5.2 BLOCK DIAGRAMFig: 5.2 BLOCK DIAGRAM5.3 MethodCarry-lookahead logic uses the concepts of?generating?and?propagating?carries. Although in the context of a carry-lookahead adder, it is most natural to think of generating and propagating in the context of binary addition, the concepts can be used more generally than this. In the descriptions below, the word?digit?can be replaced by?bit?when referring to binary addition of 2.The addition of two 1-digit inputs?A?and?B?is said to?generate?if the addition will always carry, regardless of whether there is an input-carry (equivalently, regardless of whether any less significant digits in the sum carry). For example, in the decimal addition 52 + 67, the addition of the tens digits 5 and 6?generates?because the result carries to the hundreds digit regardless of whether the ones digit carries (in the example, the ones digit does not carry (2 + 7 = 9)).In the case of binary addition,?{\displaystyle A+B}A+B?generates if and only if both?A?and?B?are 1. If we write?{\displaystyle G(A,B)}G(A,B)?to represent the binary predicate that is true if and only if?{\displaystyle A+B}A+B?generates, we have{\displaystyle G(A,B)=A\cdot B}G(A+B)=A.B;where?{\displaystyle A\cdot B}A.B?is a?logical conjunction?(i.e., an?and).The addition of two 1-digit inputs?A?and?B?is said to?propagate?if the addition will carry whenever there is an input carry (equivalently, when the next less significant digit in the sum carries). For example, in the decimal addition 37 + 62, the addition of the tens digits 3 and 6?propagate?because the result would carry to the hundreds digit?if?the ones were to carry (which in this example, it does not). Note that propagate and generate are defined with respect to a single digit of addition and do not depend on any other digits in the sum.In the case of binary addition,?{\displaystyle A+B}A+B?propagates if and only if at least one of?A?or?B?is 1. If?{\displaystyle P(A,B)}P(A,B)?is written to represent the binary predicate that is true if and only if?{\displaystyle A+B}A+B?propagates, one has{\displaystyle P(A,B)=A+B}P(A,B)=A+B;where?{\displaystyle A+B}A+B?on the right-hand side of the equation is a?logical disjunction?(i.e., an?or).Sometimes a slightly different definition of?propagate?is used. By this definition?A + B?is said to propagate if the addition will carry whenever there is an input carry, but will not carry if there is no input carry. Due to the way generate and propagate bits are used by the carry-lookahead logic, it doesn't matter which definition is used. In the case of binary addition, this definition is expressed by{\displaystyle P'(A,B)=A\oplus B}P’(A,B)=A^B;where?{\displaystyle A\oplus B}A^B?is an?exclusive or?(i.e., an?xor).For binary arithmetic,?or?is faster than?xor?and takes fewer transistors to implement. However, for a multiple-level carry-lookahead adder, it is simpler to use?{\displaystyle P'(A,B)}P’(A,B).Given these concepts of generate and propagate, a digit of addition carries precisely when either the addition generates?or?the next less significant bit carries and the addition propagates. Written in boolean algebra, with?{\displaystyle C_{i}}Ci?the carry bit of digit?i, and?{\displaystyle P_{i}}Pi?and?{\displaystyle G_{i}}Gi?the propagate and generate bits of digit?i?respectively,{\displaystyle C_{i+1}=G_{i}+(P_{i}\cdot C_{i}).}Ci+1=Gi+(Pi.Gi)5.4 Implementation DetailsFor each bit in a binary sequence to be added, the carry-lookahead logic will determine whether that bit pair will generate a carry or propagate a carry. This allows the circuit to "pre-process" the two numbers being added to determine the carry ahead of time. Then, when the actual addition is performed, there is no delay from waiting for the ripple-carry effect (or time it takes for the carry from the first?full adder?to be passed down to the last full adder). Below is a simple 4-bit generalized carry-lookahead circuit that combines with the 4-bit ripple-carry adder we used above with some slight adjustments:For the example provided, the logic for the generate (g) and propagate (p) values are given below. The numeric value determines the signal from the circuit above, starting from 0 on the far left to 3 on the far right:C1=G0+P0.C0;C2=G1+P1.C1;C3=G2+P2.C2;C4=G3+P3.C3;Substitute C1 into C2, then C2 into C3, then C3 into C4 yields the expanded equations.C1=G0+P0.C0;C2=G1+ G0.P1+ P1.P0.C0;C3=G2+G1.P2+G0.P1.P2+C0.P0.P1.P2;C4=G3+G2.P3+G1.P2.P3+G0.P1.P2.P3+C0.P0.P2.P2.P3To determine whether a bit pair will generate a carry, the following logic works: Gi=Ai.BiTo determine whether a bit pair will propagate a carry, either of the following logic statements work:Pi=Ai^Bi;Pi=Ai+Bi;The reason why this works is based on evaluation of?{\displaystyle C_{1}=G_{0}+P_{0}\cdot C_{0}}C1=G0+P0.C0. The only difference in the truth tables between ({\displaystyle A\oplus B}A^B) and ({\displaystyle A+B}A+B) is when both?{\displaystyle A}A?and?{\displaystyle B}B?are 1. However, if both?{\displaystyle A}A?and?{\displaystyle B}B?are 1, then the?{\displaystyle G_{0}}G0?term is 1 (since its equation is?{\displaystyle A\cdot B}A.B), and the?{\displaystyle P_{0}\cdot C_{0}}G0?term becomes irrelevant. The XOR is used normally within a basic full adder circuit; the OR is an alternative option (for a carry-lookahead only), which is far simpler in transistor-count terms.The carry-lookahead 4-bit adder can also be used in a higher-level circuit by having each CLA logic circuit produce a propagate and generate signal to a higher-level CLA logic circuit. The group propagate ({\displaystyle PG}PG) and group generate ({\displaystyle GG}GG) for a 4-bit CLA are:They can then be used to create a carry-out for that particular 4-bit group:It can be seen that this is equivalent to?{\displaystyle C_{4}}C4?in previous equations.Putting four 4-bit CLAs together yields four group propagates and four group generates. A?lookahead-carry unit?(LCU) takes these 8 values and uses identical logic to calculate?{\displaystyle C_{i}}Ci?in the CLAs. The LCU then generates the carry input for each of the 4 CLAs and a fifth equal to?{\displaystyle C_{16}}C16.The calculation of the?gate delay?of a 16-bit adder (using 4 CLAs and 1 LCU) is not as straight forward as the ripple carry adder.Starting at time of zero:calculation of?{\displaystyle P_{i}}Pi?and?{\displaystyle G_{i}}Gi?is done at time 1,calculation of?{\displaystyle C_{i}}Ci?is done at time 3,calculation of the?{\displaystyle PG}PG?is done at time 2,calculation of the?{\displaystyle GG}GG?is done at time 3,calculation of the inputs for the CLAs from the LCU are done at:time 0 for the first CLA,time 5 for the second, third and fourth CLAcalculation of the?{\displaystyle S_{i}}Si?are done at:time 4 for the first CLA,time 8 for the second, third & fourth CLA,calculation of the final carry bit ({\displaystyle C_{16}}C16) is done at time 5.The maximal time is 8 gate delays (for?{\displaystyle S_{[8-15]}}S[8-15]).5.5 Advantages and Disadvantages of Carry Look-Ahead Adder :5.5.1 AdvantagesThe propagation delay is reduced.It provides the fastest addition logic.5.5.2 DisadvantageThe Carry Look-ahead adder circuit gets complicated as the number of variables increase.The circuit is costlier as it involves more number of hardware.CHAPTER 6RESULT6.1 CONVENTIONAL CMOS (CARRY LOOK AHEAD ADDER) SCHEMATICFig : 6.16.2 CONVENTIONAL CMOS (CARRY LOOK AHEAD ADDER) TEST BENCHFig : 6.26.3 CONVENTIONAL CMOS (CARRY LOOK AHEAD ADDER) WAVEFORMFig : 6.36.4 ECRL (CARRY LOOK AHEAD ADDER) SCHMEATICFig: 6.46.5 ECRL (CARRY LOOK AHEAD ADDER ) TESTBENCHFig : 6.5 6.6 ECRL (CARRY LOOK AHEAD ADDER) WAVEFORMFig : 6.6CHAPTER 7CONCLUSIONSThe different parameter variations against adiabatic logic families are investigated, which shows that adiabatic logic families highly depend upon its parameter variations. But less energy consumption in adiabatic logic families can be still achieved than CMOS logic over the wide range of parameter variations. Hence adiabatic logic families can be used for low power application over the wide range of parameter variations.ECRL is a low-energy, adiabatic logic. Simulation indicates power saving over static and other adiabatic logic families. The ECRL inverter chain shows 10-20 times power gain over a conventional inverter chain. ECRL shows large power saving and shows the promising usage of ECRL in a low power system.With the adiabatic switching approach, circuit energies are conserved rather than dissipated as heat. Depending on the application and the system requirements, this approach can sometimes be used to reduce the power dissipation of digital systems.CHAPTER 7REFERENCE’SB. Dilip Kumar and M. Bharathi , “Design of Energy Efficient Arithmetic Circuit using Charge Recovery Adiabatic Logic”, International Journal Of Engg. Trends and Technology, Vol. 4, Issue-1, 2013.P.Teichmann,“Fundamentals of Adiabatic Logic”, lecture on Adiabatic Logic, Springer Series in Advanced Microelectronics 34, 2012.Jianping HU and Qi Chen, “Modelling and Near-Threshold Computing of Power- Gating Adiabatic Logic Circuits”, Electrical review, ISSN, 2012.Yangbo Wu, Jindan Chem and Jianping Hu, ‘Near-Thrshold Computing of ECRL Circuits for Ultra-Low Power application”, Advanced Electrical and Electronics Engg., LNEE87, pp.217.224, Springer-Verlag Berlin Heidelberg, 2011.Nazrul Anvar, Toshikazu Sekine, “Fundamental Logic based on Two Phased Clocked Adiabatic Static CMOS Logic”, IEEE journal of Semiconductor Technology and Science, Vol.10,No.1, 2009Laszlo Varga, Frence Kovacs, Gabor Hosszu, “An Efficient Adiabatic Charge Recovery Logic”, IEEE papers, 2001.Muhammad Arsalan, Maitham Shams, “Comparative Analysis of Adiabatic Logic Styles”, IEEE papers, INMIC 2004.Youngjoon Shin, Chanho Lee, Young Moon,“A Low-Power 16-bit RISC Microprocessor using ECRL Circuits”, ETRI Journal, Vol.26, No.6, Dec. 2004.L.A. Akers, R. Suram, “Adiabatic circuits for Low-power Logic”, IEEE papers, Aug. 2002.Atul Kumar Maurya, Ganesh Kumar, “Energy Efficient Adiabatic logic for Low-Power VLSI Application", International Conference on Communication System and Network Technologies, 2011.Neha Arora, B.P. Singh, Tripti Sharma, K.G. Sharma, Adiabatic and Standard CMOS Interfaces at 90nm Technology”, WSEAS Transactions on Circuits and Systems, Issue3, Vol. 9, March 2010.Hee-sup Song, Jin-Ku Kang,“A CMOS Adiabatic Logic for Low- Power Circuits Design”, IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Aug 200 ................
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