GBT-SCA v2.2 - CERN



GBT XE "GBT" -SCA XE "GBT-SCA" The Slow Control Adapter for the GBT XE "GBT" System Alessandro Gabrielli(Kostas Kloukinas, Paulo Moreira, Alessandro Marchioro, Sandro Bonacini, Filipe Sousa)Document History18/04/2008 Rev 1.028/04/2008 Rev 1.107/05/2008 Rev 1.226/05/2008 Rev 1.328/05/2008 Rev 1.412/06/2008 Rev 1.518/11/2008 Rev 1.627/12/2008 Rev 2.016/01/2009 Rev 2.122/05/2009 Rev 2.226/10/2010 Rev 3.020/11/2010 Rev 4.023/05/2011 Rev 4.116/06/2011 Rev 4.220/10/2011 Rev 4.322/11/2011 Rev 5.0GeneralThis document describes the GBT XE "GBT" -SCA XE "GBT-SCA" , a general-purpose integrated circuit for the monitoring and control of the electronics in HEP experiments.This document focuses on the user-visible aspects of the component such as its logical and electrical interfaces, programming features and operating modes. It also includes detailed descriptions and specifications of the chip pin-out and electrical characteristics. The Slow Control Adapter (SCA) chip is designed to work in parallel with to the GBT XE "GBT" optical link bidirectional transceiver system of which it extends the functionality.To understand the SCA in a system using GBT XE "GBT" links, a brief explanation of a GBT based system is provided in the next section. Overview of the GBT XE "GBT" SystemTypical High Energy Physics systems are today composed of three functional subsystems each of which traditionally implements its transmission system from the control room to the electronics located in the detectors. These systems are:A fast timing distribution system responsible to deliver to the experiment the system clock and several fast trigger signals, and sometimes some fast signal from the detector to the control roomA data acquisition link carrying the collected data from the detector to the control roomA Slow control system carrying bidirectional traffic from and to the control room and the embedded electronics in the detectorsThe GBT XE "GBT" project aims at providing a bidirectional system carrying all three types of traffics mentioned above. Clearly this is achieved by sharing a common medium, which in the GBT system is expected to be a pair of unidirectional optical fibers each one with a capacity of about 4.8 Gbit/s. An appropriate bandwidth is allocated to each of the three tasks in the GBT system.The slow control part is one of the subsystems served by the GBT XE "GBT" . The GBT protocol is totally transparent to the slow control protocol. The GBT encoded slow control information in the counting room, carries it along the other traffic on the optical fibers, and delivers the information unmodified to the GBT-SCA XE "GBT-SCA" in the embedded system.A block diagram of the GBT XE "GBT" system in illustrated in Figure 1The GBT XE "GBT" system consists physically of a dedicated ASIC called GBTX in the embedded electronics and of an FPGA called GBTFA containing several GBT channels in the counting room. The GBT-SCA XE "GBT-SCA" is connected physically to the GBTX, which implements the long-haul transmission medium for it.As the GBT XE "GBT" system is based on a point-to-point architecture, the slow control system consists essentially in a local area network using a point-to-point topology. The bandwidth allocated by the GBT XE "GBT" system to the slow control function is 80 Mbit/s.Figure SEQ Figure \* ARABIC 1 Control module, simplified viewThe arrangement shown in the figure assumes that the connection between the GBT13 and the GBTFA is done via optical fibers, the connections between embedded Control modules is done electrically using low voltage differential lines (LLVDS).Overview of the GBT XE "GBT" -SCA XE "GBT-SCA" ArchitectureA complete system for the control of the embedded electronics is normally composed of the following four components:A computer in a remote control room is the brain of the system: it runs an operating system and an application program that by performing remote actions on an SCA is capable of reading and writing the user registers in peripheral chips connected to the SCA peripheral ports.A transport network, in this case the GBT XE "GBT" system, carries physically information under the form of packets in a unified format between the counting room and the embedded SCA.The SCA itself is the embedded node of the system and translates the unified packets sent by the computer above into a transfer to one of the peripheral ports or an action performed by one of the embedded peripherals.The SCA has two independent e-ports to connect to the GBTs. One of the two ports is primary and must be connected in any case. The second one is to be used if two different GBTs need to share the slow-control. In this way, even if one of the two e-link brakes up, the second one can take the control of the SCA. Thus, this schema allows interfacing with one individual SCA through two different GBTs. In this way an automatic double e-port redundancy is guaranteed. A block diagram of this redundancy is shown in Figure 2.Figure SEQ Figure \* ARABIC 2 E-port RedundancyThe peripherals to the SCA are electronic components accessible via one of the buses implemented in the SCA. These buses are, for example, I2C XE "I2C" , JTAG XE "JTAG" , parallel I/O bus etc, as we will explain in detail below. In an HEP experiment these components can be front-end chips dedicated to the read-out of specific detectors, or monitoring chips for the control of environmental variables such as local voltages, temperatures etc. The communication protocol used between the control remote computer and the peripheral chips is a system is based on two layers:The first layer connects the remote control computer to the SCAs; the protocol on this layer is message based and is implemented in a way similar to standard computer LAN networks. In the GBT XE "GBT" -SCA XE "GBT-SCA" system, the GBT is completely agnostic to this protocol; packets from the remote computer to the SCA are transmitted unmodified by the GBT link.The second layer connects the SCA to the peripheral chips in the system via so called Channel Ports. The protocols used here are called the Channel Protocols.The first layer is unified and common to all SCAs, and is based on LAN architecture transporting data packets to and from the GBT XE "GBT" and remote controllers. The second layer is specific to the channel, and different kind of physical implementations of the channels are foreseen. The SCA contains the blocks as shown in Fig. 3:On the GBT XE "GBT" sideA MAC ControllerA Network Controller XE "Network Controller" (NC). The SCA internal control and status registers are seen through a special interface capable for instance to report the status of the other SCA channels.An Arbiter, based upon Round-Robin technique, to enable the user ports, the monitors or the NC, one at a time, to send data backwards towards the GBT XE "GBT" upon reply of previous requests. In this view the NC is also seen like the other ports and if a command is addressed to the NC, it sends an enable request to the Arbiter before sending data backwards.On the user side the SCA has a number of channel ports, sometimes including dedicated controllers, and organized as follows:A group of 16 I2C XE "I2C" master controllersOne JTAG XE "JTAG" master controllerA group of 4 8-bit fully programmable and bidirectional IO ports, functionally similar the ones used in the Motorola PIA XE "PIA" etc. These ports are multiplexed with the Memory Channel XE "Memory Channel" to save I/O pads. The selection is made via a hardwired input pin.One memory XE "memory" -like bus master controller with 8 bit data and 16 bit address data path, to access devices such as static memories, A/D converters etc. As stated above, this port is multiplexed with the 4 PIA XE "PIA" ports.One serial SPI XE "SPI" master bus.32 analog channels, to be used one at a time, to be converted to a 12-bit value via an ADC XE "ADC" port.4 DAC XE "DAC" 8-bit ports. 4 asynchronous external interrupts XE "interrupts" . These interrupts are continuously polled by the NC that provides a dedicated packet backwards to the GBT XE "GBT" to let the users aware of the interrupt requests. The communication between these user accessible ports and the Network Controller XE "Network Controller" handling the high level protocol with the remote computer is done via appropriate internal buses and is not visible by the user of the SCA.The dual network layer architecture introduced above is necessary to support applications where long cables/fibers are used between the control room of the experiment and the embedded SCA (therefore generating long delays) and to support the relatively slow buses chosen to interface to the front end chips, such as the I2C XE "I2C" bus. This architecture assumes that the control is done by sending data packets (messages) to the respective channels, which interpret the messages as commands, execute them on their external interfaces (for example just a read or write operation to a memory XE "memory" bus) and return a status reply to the GBT XE "GBT" via another message. The commands can be either addressed to registers located within the channel ports – configuration registers – or to devices located in the far front-end. In this latter case the command interpretation and execution is demanded to the front-end electronics.This protocol assumes that the remote devices controlled by the SCAs are seen from the control computer as remote independent channels, each one with a particular set of control registers and/or allocated memory XE "memory" locations. The channels operate independently from each other to allow concurrent transactions. The channels can perform transfers to their end-devices concurrently.To decouple the operation on the channel ports with respect to the one of the GBT XE "GBT" link, the architecture assumes that all operations on the channels are asynchronous and do not demand an immediate response. Basically this means that all commands carried by the GBT link under the form of network messages are posted to the channel interfaces. This is easy to implement for write operations, where practically one works by posting write operations to the channels. For read operations a read request is sent to the channel; the channel performs the operation on its interface and returns a request of attention to the Arbiter. All upwards packets are acknowledged via either status or data words depending on the command type. Read commands send data backwards, which are auto-acknowledged; write commands send just the status of the channel as a backward reply.Figure 3 shows the GBT XE "GBT" -SCA XE "GBT-SCA" architecture as described above. A few details concerning the internal channels are also provided. Figure 4 instead shows a block schema of the MAC controller.Figure 4 shows the Reset Tree XE "Reset Tree" of the SCA. In particular the chip and internal blocks can be reset in different ways via:an external asynchronous reset pin that resets the entire chip,a GBT command to the MAC controller. In this way all the blocks except the MAC controller are reset as it was used the external asynchronous reset pin,a GBT command delivered through the NC to the uniquely addressed IO port,a GBT command to the NC that is broadcasted to all the IO ports except the Arbiter.Figure SEQ Figure \* ARABIC 3: block diagram of the GBT XE "GBT" -SCA XE "GBT-SCA" : Figure SEQ Figure \* ARABIC 4: Logic Reset Tree XE "GBT-SCA" of the GBT-SCAFigure SEQ Figure \* ARABIC 5: MAC to Network Controller XE "Network Controller" interfaceRadiation tolerance featuresTo be able to operate in an LHC environment, the SCA is designed with some rad-tolerant features. These features include:Resistance to high total ionizing dose (TID) as required by LHC electronic systemsInclusion of triple redundant circuitry on some critical logic blocks for single event effects (SEE) robustness.Critical control state machines and logic are protected by redundancy. This will be implemented using either spatial or temporal redundancy as required.The data path on the SCA instead is not protected by redundancy and errors that will occur due to SEE will be detected through parity mechanisms. Such errors are not critical for the operation of the SCA, as corrupted commands can be re-executed by the remote controlling software.SCA PACKET descriptionThe protocolThe SCA exchanges information with the remote computer using as transport layer the GBT XE "GBT" link. The packets exchanged along this route are of a unified format. The remote computer typically initiates all actions by sending some commands to the SCA which then translates this command into an action to be performed onto one of its peripheral ports.The connection between the remote computer and the embedded SCA is of a point-to-point type therefore no addressing information is needed to be dispatched to the SCA along the GBT XE "GBT" link.To acknowledge reception of each command packet, the SCA returns the received packet to the remote computer. In this way the remote computer knows that the command has been received at the destined SCA.The link between the SCA and the computer (through the GBT XE "GBT" ) exchanges only two types of packets:IDLE: when no useful information is to be sent, an idle is inserted by the transmitter and discarded at the receiver. This packet is a single byte long.DATA: Useful information is instead encapsulated in a structure which is defined as follows:A Start Of Frame (SOF) bytePAYLOAD bytesA CRC XE "CRC" byteAn End Of Frame (EOF) byteThe length of this packet is variable and delimited by the EOF byte. The MAC reads also the content of the LEN byte (see below) in the PAYLOAD and checks that the length of the packet is correct by verifying that the last byte is indeed an EOF byte. The MAC also verifies the correctness of the CRC XE "CRC" .The MAC adapter strips the SOF, CRC XE "CRC" and EOF at the input of the SCA, and only the PAYLOAD content is delivered to the internal part of the SCA. The SCA can also generate packets to the control computer. Such messages are generated, for instance, upon generation of an interrupt in the SCA and upon completion of a read operation on an external peripheral port. In any case the SCA acknowledges the packets coming from the GBT XE "GBT" via a so-called acknowledge packet. Figure 5 shows the forward and backward packet communications.When not transmitting useful data packets, the SCA generates idle packets. These idle packets are the same in both directions.Figure SEQ Figure \* ARABIC 6: SCA Packet communication systemPAYLOAD FormatThe content of the PAYLOAD section is depicted below:CH#TR#CMDDATAOptional (LEN)1 byte1 byte1 byte1 to N bytesFigure SEQ Figure \* ARABIC 7: SCA-to-Port Command Packet exampleFigure 6 shows how a command is sent to a specific port. In any case a reply - Fig. 7 - is foreseen and this is sent back with a different PAYLOAD. In particular, the ACK byte is used to state the command status. In this way is the command has been correctly received by the addressed port is visible through the ACK byte. Only the RESET commands sent to the ports are not acknowledged with a reply packet.CH#TR#ACKDATA1 byte1 byte1 byte1 to N bytesFigure SEQ Figure \* ARABIC 8: Port-to-SCA Reply Packet exampleThis is delivered by the SCA Node Controller to the channel identified by the CHAN field.The different field are defined as follows::CH# specifies the SCA internal port to be addressed – i.e. I2C XE "I2C" , JTAG XE "JTAG" , NC, SPI XE "SPI" , etc. -,TR# is a byte used to identify the operation being carried out. This value is returned during the acknowledgement of completion of operations by the SCA to the remote computer. CMD is a command code that specifies a given operation to be performed on a channel port. The operation can refer to a specific internal register of the channel – i.e. a configuration register – or to a n external bus related operation, such as, for example, an I2C XE "I2C" read or write. In this case an address field follows the command.DATA is a command dependent variable length field.LEN is an optional field that specifies the PAYLOAD length and can be considered as part of the DATA field. It is only used for I2C channels and accepts values from 1 to 28 depending on the commands: if the commands is the multiple write in extended addressing mode, i.e. two bytes are used for the address, 26 bytes can be written at most. On the contrary, if the command is the multiple write with normal addressing mode, i.e. one byte only is used for the address, then 27 bytes are available for writing.ChannelS IN GBT XE "GBT" -SCA XE "GBT-SCA" GeneralChannels receive commands from the node controller and control the actions on the bus to which they connect as masters. These commands are contained in the data packet and therefore data contents, in a given packet, interpreted differently by each channel. The command sub-field (typically the third byte in a message to a channel) contains the code for the requested operation. Each channel has a set of valid commands as explained in this chapter. Channels receiving an invalid command do not execute any action and report the error condition to the node controller.Upon reception of a command a channel performs the required operation on its interface and then, depending on the specifics of the command, can return a reply to the node controller as a data block, which is then transmitted, to the destination in a message packet. The distinction between channels at the level of the GBT XE "GBT" is performed essentially by software.The following paragraphs specify the content of the packets for each type of channel.In this implementation, the GBT XE "GBT" -SCA XE "GBT-SCA" does not support command queuing for the I2C XE "I2C" channels. Only one command can be in execution at any one time.Allocations of channels in the GBT XE "GBT" -SCA XE "GBT-SCA" Each channel in a network data packet (message) is identified by the first data byte in the data payload. The following table gives the internal address allocation for channels in the GBT XE "GBT" -SCA XE "GBT-SCA" :Channel Number XE "Channel Number" [Hex]Function0x00Network Controller XE "Network Controller" 0x02Master SPI XE "SPI" (Serial Peripheral Interface)0x10?0x1FMaster I2C XE "I2C" Channels (16 identical)0x30?0x33Master PIA XE "PIA" Channels (4 identical)0x40Master Memory Channel XE "Memory Channel" 0x60Master JTAG XE "JTAG" Channel0x701 out of 32 selectable Analog Input Channels (ADC XE "ADC" )0x80?0x83DAC XE "DAC" Analog Output Channel (4 identical)0xAASCA Reset XE "SCA Reset" channel, if combined with 0xAA command0xFCInterrupt Channel XE "Interrupt Channel" 0, not addressable, active low0xFDInterrupt Channel XE "Interrupt Channel" 1, not addressable, active low0xFEInterrupt Channel XE "Interrupt Channel" 2, not addressable, active low0xFFInterrupt Channel XE "Interrupt Channel" 3, not addressable, active lowFigure SEQ Figure \* ARABIC 9: Channel number allocationThe 0xFC-0xFF addresses are Reserved for the interrupts XE "interrupts" so cannot be used for CH#. 0xFF is then a Reserved TR# ID.GBT XE "GBT" -SCA XE "GBT-SCA" controllerThe GBT XE "GBT" -SCA XE "GBT-SCA" controller is a dedicated logic block inside each GBT-SCA, which is needed mainly for network and internal channels supervision. The GBT-SCA controller is reachable with the same protocol used to transfer data to the other port channels.The following registers are defined in the controller:NameFunctionCRA XE "CRA" Control Register A - generalCRBControl Register B – I/O Port Enable – default is 0, disabledCRC XE "CRC" Control Register C – I/O Port Enable – default is 0, disabledCRD XE "CRD" Control Register D – I/O Port Enable – default is 0, disabledCRE XE "CRE" Control Register E – I/O Port Enable – default is 0, disabledSRA XE "SRA" Status Register ASRB XE "SRB" Status Register BFigure SEQ Figure \* ARABIC 10: Control and Status registers in GBT XE "GBT" -SCA XE "GBT-SCA" ControllerControl registers are all read/write registers. They can be read back after a write operation to verify their contents. Status registers are read-only registers, as they are set typically by hardware inside the GBT XE "GBT" -SCA XE "GBT-SCA" .Control Register AControl register A is a general control register for the GBT XE "GBT" -SCA XE "GBT-SCA" . It contains control bits, which are relevant for the operation of all channels in the GBT-SCA.The following bits are defined:BitNameFunctionComment0MEM_PIA XE "PIA" Memory vs PIA XE "PIA" selectionDefault at 0 to select the 4 PIA XE "PIA" ports. When at 1 Memory channel is available1-4Reserved5EXTRESGenerates external resetWriting a “1” to this bit generates a 10 μs reset pulse on the Reset_Out XE "Reset_Out" pin. This bit is always read back as “0”.Read as a “1” during the reset time.6Reserved7ReservedFigure SEQ Figure \* ARABIC 11 Network Controller XE "Network Controller" control register AControl Register B-C-D-EThe node controller Control registers B-C-D-E are defined to enable, individually, the ports in such a way that if any port is disabled, it does not receive the clock. In this way the power consumption can be reduced at the lowest value according to the user constraints. By default all the ports are disabled.BitNameFunctionCommentB-0 B0 Enable port I2C XE "I2C" -0 Enable address 0x10B-1 B1 Enable port I2C XE "I2C" -1 Enable address 0x11B-2 B2 Enable port I2C XE "I2C" -2 Enable address 0x12B-3 B3 Enable port I2C XE "I2C" -3 Enable address 0x13B-4 B4 Enable port I2C XE "I2C" -4 Enable address 0x14B-5 B5 Enable port I2C XE "I2C" -5 Enable address 0x15B-6 B6 Enable port I2C XE "I2C" -6 Enable address 0x16B-7 B7 Enable port I2C XE "I2C" -7 Enable address 0x17C-0 C0 Enable port I2C XE "I2C" -8 Enable address 0x18C-1 C1 Enable port I2C XE "I2C" -9 Enable address 0x19C-2 C2 Enable port I2C XE "I2C" -10 Enable address 0x1AC-3 C3 Enable port I2C XE "I2C" -11 Enable address 0x1BC-4 C4 Enable port I2C XE "I2C" -12 Enable address 0x1CC-5 C5 Enable port I2C XE "I2C" -13 Enable address 0x1DC-6 C6 Enable port I2C XE "I2C" -14 Enable address 0x1EC-7 C7 Enable port I2C XE "I2C" -15 Enable address 0x1FD-0 D0 Enable port JTAG XE "JTAG" Enable address 0x60D-1 D1 Enable port SPI XE "SPI" Enable address 0x02D-2 D2 Enable port Memory Enable address 0x40D-3 D3 Enable port ADC XE "ADC" Enable address 0x70D-4 D4 Enable port PIA XE "PIA" -A Enable address 0x30D-5 D5 Enable port PIA XE "PIA" -B Enable address 0x31D-6 D6 Enable port PIA XE "PIA" -C Enable address 0x32D-7 D7 Enable port PIA XE "PIA" -D Enable address 0x33E-0 E0 Enable port DAC-0 XE "DAC" Enable address 0x80E-1 E1 Enable port DAC-1 XE "DAC" Enable address 0x81E-2 E2 Enable port DAC-2 XE "DAC" Enable address 0x82E-3 E3 Enable port DAC-3 XE "DAC" Enable address 0x83E-4 E4 Enable port Interrupt0 Enable address 0xFCE-5 E5 Enable port Interrupt1 Enable address 0xFDE-6 E6 Enable port Interrupt2 Enable address 0xFEE-7 E7 Enable port Interrupt3 Enable address 0xFFFigure SEQ Figure \* ARABIC 12 Control register B-C-D-E in Network ControllerStatus Register AThe node controller status register A is defined as follows:BitNameFunction0Err CHN XE "Err CHN" Flag Error invalid channel1Err ERR XE "Err ERR" Flag Error error bit on AI2Err TR XE "Err TR" Flag Error invalid Transaction (FF is Reserved for Interrupts)3Err CMDFlag Error invalid command4-6 7GE XE "GE" This bit is the global OR of all error bits generated in any channel in the GBT XE "GBT" -SCA XE "GBT-SCA" .Figure SEQ Figure \* ARABIC 13 Node Controller status register AStatus Register BThe status register B is an 8-bit register containing the transaction number (TR#) of the last correctly received command for any of the GBT XE "GBT" -SCA XE "GBT-SCA" channels. This is necessary to support the case when a packet traveling through the network gets corrupted after having reached the destination and the GBT has to find out whether the packet had already reached its destination or mand codesThe following table summarizes the commands accepted by the node controller for operations on its registers. Below CH# is 0x40 except for “SCA Reset XE "SCA Reset" ”.CommandCMD[Hex]Command andReply FormatsOperationWrite CRA XE "CRA" 0x00C: CH# + TR# + CMD + DWR: CH# + TR# + ACK + CRA XE "CRA" The CRA XE "CRA" is written with a byteWrite CRB0x01C: CH# + TR# + CMD + DW R: CH# + TR# + ACK + CRBThe CRB is written with a byteWrite CRC XE "CRC" 0x02C: CH# + TR# + CMD + DWR: CH# + TR# + ACK + CRC XE "CRC" The CRB is written with a byteWrite CRD XE "CRD" 0x03C: CH# + TR# + CMD + DW R: CH# + TR# + ACK + CRD XE "CRD" The CRC XE "CRC" is written with a byteWrite CRE XE "CRE" 0x04C: CH# + TR# + CMD + DW R: CH# + TR# + ACK + CRE XE "CRE" The CRE XE "CRE" is written with a byteRead CRA XE "CRA" 0x10C: CH# + TR# + CMD R: CH# + TR# + ACK + CRA XE "CRA" Read CRA XE "CRA" Read CRB0x11C: CH# + TR# + CMD R: CH# + TR# + ACK + CRBRead CRBRead CRC XE "CRC" 0x12C: CH# + TR# + CMD R: CH# + TR# + ACK + CRC XE "CRC" Read CRC XE "CRC" Read CRD XE "CRD" 0x13C: CH# + TR# + CMD R: CH# + TR# + ACK + CRD XE "CRD" Read CRD XE "CRD" Read CRE XE "CRE" 0x14C: CH# + TR# + CMD R: CH# + TR# + ACK + CRE XE "CRE" Read CRE XE "CRE" Read SRA XE "SRA" 0x20C: CH# + TR# + CMDR: CH# + TR# + ACK + SRA XE "SRA" Send back the status register ARead SRB XE "SRB" 0x21C: CH# + TR# + CMDR: CH# + TR# + ACK + SRB XE "SRB" Send back the status register BReset0xFFC: CH# + TR# + CMDR:noneReset the NCSCA Reset XE "SCA Reset" 0xAAC: CH#=0xAA + TR# + CMD=0xAAR:noneReset the NC and all the front-end portsFigure SEQ Figure \* ARABIC 14 Commands for the Network Controller XE "Network Controller" i2c channelGeneralThe I2C XE "I2C" interface implements normal 7 bit addressing, long 10 bit addressing I2C transactions and extended RAL mode transfers. The operations performed by the I2C interface are:Single byte read-write with normal 7 bit I2C XE "I2C" addressingSingle byte read-write extended I2C XE "I2C" with 10 bits addressing Multi byte read-write extended I2C XE "I2C" with 10 bits addressing I2C XE "I2C" interface registersSeveral registers control the operation of the I2C XE "I2C" interface and are implemented in each of the 16 I2C channels. The registers are cleared at reset. NameCommentCRA XE "CRA" Control register AMSK XE "MSK" Mask register for logical operationsSRA XE "SRA" Status register ASRB XE "SRB" Status register BFigure SEQ Figure \* ARABIC 15 Control and Status registers in I2C XE "I2C" channelI2C XE "I2C" Control registersThe Control register A in the I2C XE "I2C" interface is defined as follows:BitNameFunction1-0SPEEDDenotes the speed of operation of the I2C XE "I2C" interface (SCL clock rate):00 – 100 kHz01 – 200 kHz10 – 400 kHz11 – 1 MHz2-4 ----- Reserved5EBRDCSTEnable broadcast operations. Once set to “1” this bit enables the channel to accept I2C XE "I2C" broadcast operations. This bit is initialised to “0” after reset.6FACKWForce acknowledge for write or RMW operationWrite operations and RMW operations, which do not generate errors, are not acknowledged. Setting this bit to “1” forces an acknowledgement packet. This bit is cleared at reset.7 ----- ReservedFigure SEQ Figure \* ARABIC 16 Control register A in I2C XE "I2C" interfaceLogical mask registerThis register can be written with an 8-bit value, which is used during logical operations on the I2C XE "I2C" bus. Read-modify-write operations and can only be executed in single-byte mode. Three basic operations are allowed: Logical AND, Logical OR, Logical XOR and are performed in the following way:the I2C XE "I2C" interface reads a byte from the specified addressa logical operation is performed with the mask register valuethe result is written back into the I2C XE "I2C" addressthe original value is returned to the GBT XE "GBT" (if CRA XE "CRA" [6] is set).I2C XE "I2C" Status RegistersSeveral registers are used to report the status of the I2C XE "I2C" channelStatus Register AThis register contains the following information:BitNameFunction0Flag_error_Byte2NCThis bit reports the reply from the I2C XE "I2C" port to the NC. It is set if the reply word to the NC fails.1Flag_error_PortBusyThis bit reports I2C XE "I2C" port busy status. If a new command arrives when the port is still busy the flag is set.2SUCCThis bit is set when the last I2C XE "I2C" transaction was successfully executed.3I2CLOWThis bit is set to ‘1’ if the I2C XE "I2C" master port finds that the SDA line is pulled low (“0”) before initiating a transaction. If this happens the I2C bus is probably broken. The bit represents the status of the SDA line and cannot be reset.4Flag_error_rwThis bit is set if the commands that requires a specific code for read and write operations make conflicts the command code.5INVCOM XE "INVCOM" This bit is set if an invalid command was sent to the I2C XE "I2C" channel. The bit is cleared by a channel reset.6NOACK XE "NOACK" This bit is set if the last operation has not been acknowledged by the I2C XE "I2C" slave acknowledge. This bit is set/reset at the end of each I2C transaction7GE XE "GE" This bit is set if any error has occurred on the I2C XE "I2C" channel and is cleared only by a channel reset commandFigure SEQ Figure \* ARABIC 17 Status register A in I2C XE "I2C" interfaceStatus Register BStatus register B contains the number of the last correctly executed transaction (TR#). This register is overwritten after every I2C XE "I2C" transaction except read and write operations to/from the control and status register. I2C XE "I2C" CommandsThe following table summarizes all the commands accepted by the I2C XE "I2C" channels. Below CH# is 0x10-0x1F except for “SCA Reset XE "SCA Reset" ”.CommandCMD[Hex]Command and Reply FormatSingle byte write normal mode0x00C: CH# + TR# + CMD + A[7:0] + DWR: CH# + TR# + ACK + DRSingle byte read normal mode0x01C: CH# + TR# + CMD + A[7:0]R: CH# + TR# + ACK + DRSingle byte write extended mode0x02C: CH# + TR# + CMD + A[9:8] + A[7:0] + DWR: CH# + TR# + ACK + DRSingle byte read extended mode0x03C: CH# + TR# + CMD + A[9:8] + A[7:0]R: CH# + TR# + ACK + DRRMW-AND in normal mode0x80C: CH# + TR# + CMD + A[7:0]R: CH# + TR# + ACK + DRRMW-OR in normal mode0x81C: CH# + TR# + CMD + A[7:0]R: CH# + TR# + ACK + DRRMW-XOR in normal mode0x82C: CH# + TR# + CMD + A[7:0]R: CH# + TR# + ACK + DRRMW-AND in extended mode0x83C: CH# + TR# + CMD + A[9:8] + A[7:0]R: CH# + TR# + ACK + DRRMW-OR in extended mode0x84C: CH# + TR# + CMD + A[9:8] + A[7:0]R: CH# + TR# + ACK + DRRMW-XOR in extended mode0x85C: CH# + TR# + CMD + A[9:8] + A[7:0]R: CH# + TR# + ACK + DRMultiple Byte Write in extended mode (LEN <=28=2xA+26xDW)0x86C: CH# + TR# + CMD + LEN + A[9:8] + A[7:0] + DW R: CH# + TR# + ACK + DRMultiple Byte Read in extended mode (LEN <=28=2+26)0x87C: CH# + TR# + CMD + LEN + A[9:8] + A[7:0]R: CH# + TR# + ACK + DR (LEN -2 bytes)Multiple Byte Write in normal mode (LEN <=28=1xA+27xDW)0x88C: CH# + TR# + CMD + LEN + A[7:0] + DW R: CH# + TR# + ACK + DRMultiple Byte Read in normal mode (LEN <=28=1-A+27-DR)0x89C: CH# + TR# + CMD + LEN + A[7:0]R: CH# + TR# + ACK + DR (LEN -1 bytes)Write Control register A0xf0C: CH# + TR# + CMD + DWR: CH# + TR# + ACK + DRRead Control register A0xf1C: CH# + TR# + CMDR: CH# + TR# + ACK + DRRead Status register A0xf2C: CH# + TR# + CMDR: CH# + TR# + ACK + DRRead Status register B0xf3C: CH# + TR# + CMDR: CH# + TR# + ACK + DRWrite Mask register0xf6C: CH# + TR# + CMD + DWR: CH# + TR# + ACK + DRRead Mask register0xf7C: CH# + TR# + CMDR: CH# + TR# + ACK + DRI2C XE "I2C" channel reset0xffC: CH# + TR# + CMDR:noneSCA Reset XE "SCA Reset" 0xAAC: CH#=0xAA + TR# + CMD=0xAA R: noneReset the NC and all the front-end portsFigure SEQ Figure \* ARABIC 18 Commands for I2C XE "I2C" channelADC Channel XE "GBT-SCA" GeneralADC XE "ADC" CommandsThe commands used for operating the ADC XE "ADC" interface are defined in this paragraph. Below CH# is 0x70 except for “SCA Reset XE "SCA Reset" ”.ActionCMD[Hex]Command Packet FormatADC XE "ADC" Reset channel0xFFC: CH# + TR# + CMDR: noneWrite control register XE "Write control register" 0xF0C: CH# + TR# + CMD + DWR: CH# + TR# + ACK + CRRead Control Register XE "Read Control Register" 0xF1C: CH# + TR# + CMDR: CH# + TR# + ACK + CRRead Status Register XE "Read Status Register" 0xF2C: CH# + TR# + CMDR: CH# + TR# + ACK + SRWrite ADC XE "ADC" register0xF3C: CH# + TR# + CMD + ADR<X,X,5:0> + DATAR: CH# + TR# + ACK + SRRead ADC XE "ADC" register0xF4C: CH# + TR# + CMD + ADR<X,X,5:0>R: CH# + TR# + ACK + DRSCA Reset XE "SCA Reset" 0xAAC: CH#=0xAA + TR# + CMD=0xAA R: noneReset the NC and all the front-end portsFigure SEQ Figure \* ARABIC 19 ADC channel CommandsNB. Here the ADC XE "ADC" Reset and SCA Reset XE "SCA Reset" commands force the ADC internal channel to be reset for 20 clock cycles.There are 32 external inputs for the ADC XE "ADC" module plus 2 internal channels - 6-bit addressing - for temperature and supply voltage monitoring.The architecture of the ADC XE "ADC" is shown in Figure 32.center145415Figure SEQ Figure \* ARABIC 20 SCA_ADC XE "ADC" architectureADC XE "ADC" BlocksThe ADC XE "ADC" contains the following main blocks:a wishbone slave interface,a bandgap voltage reference,a 12-bit ADC XE "ADC" ,calibration registers,conversion and Calibration XE "Calibration" Logica set of fuses that fixes the bandgap voltage reference.The access to the internal registers of the ADC XE "ADC" is available through a wishbone interface. The user can select one of the ADC input channels, start an ADC acquisition and read the ADC output simply by accessing different registers.A bandgap voltage reference gives to the ADC XE "ADC" a stable reference voltage which can be adjusted for a specific voltage by fusing the fuses. The reference voltage can also be adjust by adjusting the value of the bandgap register.Specifications Digital interface I/O: Wishbone Standard ProtocolOperating temperature range: -50°C -> +80°CPower consumption: < X??XmW (VDD = 1.2V, T = 25°C ? I = X??X mA) ?????Supply voltage: single VDD @ 1.2VClock frequency: 40MHzSCA_ADC XE "ADC" Internal Registers The ADC XE "ADC" contains thirteen user-accessible registers, which are listed in REF _Ref263925239 \h \* MERGEFORMAT Table 1. Three registers [SREG XE "SREG" , DLREG XE "DLREG" , and DHREG XE "DHREG" ] are read only. All the others are write/read. However only ICREG XE "ICREG" and CALREG XE "CALREG" can be written at any time, the others may be written with some time restriction [see details on the definition of each registers]. To address a specific register 4 bits are used, the address for each register is indicated on the table below.Wishbone address ADR_I<3:0>Register nameDefault content[after reset]00000Status RegisterSREG XE "SREG" -10001Control RegisterCREG XE "CREG" 0000_000020010Input Channel RegisterICREG XE "ICREG" 0000_000030011Data High RegisterDHREG XE "DHREG" 0000_000040100Data Low RegisterDLREG XE "DLREG" 0000_000050101Calibration XE "Calibration" RegisterCALREG XE "CALREG" 0000_000060110BandgapCal High RegisterBGHREG XE "BGHREG" <fuses>70111BandgapCal Low RegisterBGLREG XE "BGLREG" <fuses>81000GmCal XE "GmCal" High RegisterGMHREG0000_000191001GmCal XE "GmCal" Low RegisterGMLREG1111_1111101010IdCal High RegisterIDHREG0000_0001111011IdCal Low RegisterIDLREG1111_1111121100Test RegisterTREG XE "TREG" 0000_0000Table SEQ Table \* ARABIC 1. The SCA_ADC XE "ADC" register fileStatus Register (SREG XE "SREG" )The Status Register is used to inform the user of the actual state of the converter.Bit(s)NameDescription7ready If “1” ready for a new conversion6doneIf “1” conversion is finished and the value is available in DATA5calibratingCalibration XE "Calibration" in progress4convertingConversion in progress3sleepingIf “1” ADC XE "ADC" is in power save mode2testingIf “1” ADC XE "ADC" is in test mode<1:0>UNUSEDTable SEQ Table \* ARABIC 2. Bit assignment of Status register (SREG XE "SREG" ).ready: when [SREG XE "SREG" <7> = “1”] the ADC XE "ADC" is prepared to follow a new command. done:if [SREG XE "SREG" <6> = “1”] it means that the value on the Data registers is ready to be fetched. Otherwise the value on DHREG XE "DHREG" and DLREG XE "DLREG" are not meaningful.calibrating, converting, sleeping: reports the actual state of the converter.Control Register (CREG XE "CREG" ) [write/read]This register is used to control the converter. This registers can only be written when [SREG XE "SREG" <7> = “1”] or [SREG<3> = “1”], this is, the converter is “ready” or in “power save” state.Bit(s)NameDescription7RESET“1” to reset and after it is automatically set to “0” after reset6WAKE UP“1” to end the “power save” mode5CALIBRATE“1” to calibrate the ADC XE "ADC" and in the end is automatically set to “0”4CONVERT“1” to start an A to D conversion and in the end is automatically set to “0”3SLEEP“1” to set ADC XE "ADC" in “Power save” mode<2:0>TEST MODE“111” to start test modeTable SEQ Table \* ARABIC 3. Bit assignment of Control register (CREG XE "CREG" ).reset: setting this bit to “1” all the register will be set to their default value. This bit is also set automatically to “0” during the reset state.wake_up : setting [CREG XE "CREG" <6> = “1”] when the ADC XE "ADC" is in “power save” state will make the ADC leave that same state. Otherwise the bit CREG<6> will have no effect. In both cases the bit is set “0” on the following clock cycle.calibrate: when [CREG XE "CREG" <5> = “1”] the converter will start the calibration routine if the converter is “ready ” [SREG XE "SREG" <5> = “7”]. After the calibration routine start the bit is set to “0”.convert: when [CREG XE "CREG" <4> = “1”] the converter will start the calibration routine if the converter is “ready ” [SREG XE "SREG" <5> = “7”] and [CREG<5> = “0”]. After the calibration routine start the bit is set to “0”.sleep: if [CREG XE "CREG" <3> = “1”] and only when [CREG<5> = CREG<4>= “0”] the converter will enter in the “power save” state. This bit is only set to “0” by the user or if the converter is reset. Which means that while this bit is “1” and if no more command are to be done the converter will enter/stay in the power mode state.test_mode: when [CREG XE "CREG" <2:0> = “1”] the test mode is enable. Input Channel Register (ICREG XE "ICREG" )This register will select the input channel from which the ADC XE "ADC" will convert.Bit(s)NameDescription<7:6>UNUSED<5:0>CHANNELSelects the ADC XE "ADC" input channelTable SEQ Table \* ARABIC 4. Bit assignment of Input channel register (ICREG XE "ICREG" ).Data High/Low RegistersWhen [SREG XE "SREG" <6> = “1”] the value stored in DATA is the result of the last acquisition.RegisterBit(s)NameDHREG XE "DHREG" <7:5>UNUSED<4:0>DATA<12:8>DLREG XE "DLREG" <7:0>DATA<7:0>Table SEQ Table \* ARABIC 5. Bit assignment of Data High and Low registers (DHREG XE "DHREG" /DLREG XE "DLREG" ).Calibration XE "Calibration" Register (CALREG XE "CALREG" ) Bit(s)NameDescription7Enable_bgCal“1” to use bgCal instead of fuses6Enable_gmCal“1” to allow the user to write into gmCal register5Enable_idCal“1” to allow the user to write into idCal register<4:0>UNUSEDTable SEQ Table \* ARABIC 6. Bit assignment of Calibration XE "Calibration" register (CALREG XE "CALREG" ).Enable_bgCal: when set [SREG XE "SREG" <7> = “1”] bits {BGHREG XE "BGHREG" <1:0>, BGLREG XE "BGLREG" <7:0>} can be changed to set the badgap voltage to another value.Enable_gmCal : when set [SREG XE "SREG" <6> = “1”] bits {GMHREG<1:0>, GMLREG<7:0>} can be changed to set another value for the maximum charge current.Enable_idCal : when set [SREG XE "SREG" <5> = “1”] bits {BGHREG XE "BGHREG" <1:0>, BGLREG XE "BGLREG" <7:0>} can be changed to set the another value for the maximum discharge current.BandgapCal High/Low Registers:RegisterBit(s)NameBGHREG XE "BGHREG" <7:2>UNUSED<1:0>bgCal <9:8>BGLREG XE "BGLREG" <7:0>bgCal<7:0>Table SEQ Table \* ARABIC 7. Bit assignment of BandgapCal High and Low registers (BGHREG XE "BGHREG" /BGLREG XE "BGLREG" ).GmCal XE "GmCal" High/Low Registers RegisterBit(s)Function/internal signalsGMHREG<7:2>UNUSED<1:0>gmCal <9:8>GMLREG<7:0>gmCal<7:0>Table SEQ Table \* ARABIC 8. Bit assignment of GmCal XE "GmCal" High and Low registers (GMHREG/GMLREG).IdCal High/Low Registers RegisterBit(s)Function/internal signalsIDHREG<7:2>UNUSED<1:0>idCal <9:8>IDLREG<7:0>idCal<7:0>Table SEQ Table \* ARABIC 9. Bit assignment of IdCal High and Low registers (IDHREG/IDLREG). Test Register (TREG XE "TREG" ) The bit allocation of the Test Register is described below:Bit(s)NameFunction<7:3>UNUSED2noWaitWhen “1” the change from the charging phase to the discharge phase is made in one clock cycle, this is, without having a clock cycle where the capacitor is not charging nor discharging 1noGMIf testing mode is active this bit should be set equal to CALREG XE "CALREG" <6>0noIDIf testing mode is active this bit should be set equal to CALREG XE "CALREG" <5>Table SEQ Table \* ARABIC 10. Bit assignment of Test register (TREG XE "TREG" ).noWait : when set [TREG XE "TREG" <2> = “1”] the change from the charging phase to the discharge phase is made in one clock cycle, this is, without having a clock cycle where the capacitor is not charging nor discharging.noGM, noID : When both are “1” and if test mode active no calibration routine is performed. Register Access via the wishbone busWISHBONE is a system-on-Chip (SOC) interconnection architecture for portable IP cores, which define parallel communication protocol between IP cores. CITATION Wis02 \l 1033 (1) The ADC XE "ADC" has a Wishbone Slave Interface that allows the user to read and write on the registers.Interface description: Input PinActivityDescriptionCLK_I–Clock inputRST_IHIGHSynchronous resetWE_IHIGHWrite Enable input indicates the current local bus cycle: HIGH for write cycles, LOW for read cyclesCYC_IHIGHCycle input indicates that a valid bus cycle is in progress.STB_IHIGHStrobe input indicates that the slave is selected.ADR_I[3:0]–Address input busDAT_I[7:0]–Unidirectional data input busOutput PinActivityDescriptionACK_OHIGHAcknowledge output indicates the termination of a normal bus cycleDAT_O[7:0]–Unidirectional data output bus4114800273050Figure SEQ Figure \* ARABIC 21 Single read cycle00Figure SEQ Figure \* ARABIC 21 Single read cycleTable SEQ Table \* ARABIC 11. Wishbone signalsSupported cyclesSINGLE READ Cycle XE "SINGLE READ Cycle" The figure shows a SINGLE READ cycle. The bus protocol works as follows:CLOCK EDGE 0: MASTER presents a valid address on [ADR_I()] .MASTER negates [WE_I] to indicate a READ cycle.MASTER asserts [CYC_I] to indicate the start of the cycle.MASTER asserts [STB_I] to indicate the start of the phase.SETUP, EDGE 1: SLAVE decodes inputs, and responding SLAVE asserts [ACK_O].SLAVE presents valid data on [DAT_O()].SLAVE asserts [ACK_O] in response to [STB_I] to indicate valid data.411480096520Figure SEQ Figure \* ARABIC 22 Single write cycle00Figure SEQ Figure \* ARABIC 22 Single write cycleMASTER monitors [ACK_O], and prepares to latch data on [DAT_O()].CLOCK EDGE 1: MASTER latches data on [DAT_O()] .MASTER negates [STB_I] and [CYC_I] to indicate the end of the cycle.SLAVE negates [ACK_O] in response to negated [STB_I].SINGLE WRITE Cycle XE "SINGLE WRITE Cycle" The figure shows a SINGLE WRITE cycle. The bus protocol works as follows:CLOCK EDGE 0: MASTER presents a valid address on [ADR_I()].MASTER presents valid data on [DAT_I()].MASTER asserts [WE_I] to indicate a WRITE cycle.MASTER asserts [CYC_I] and to indicate the start of the cycle.MASTER asserts [STB_I] to indicate the start of the phase.SETUP, EDGE 1: SLAVE decodes inputs, and responding SLAVE asserts [ACK_O].SLAVE prepares to latch data on [DAT_I()].SLAVE asserts [ACK_O] in response to [STB_I] to indicate latched data.MASTER monitors [ACK_O], and prepares to terminate the cycle.CLOCK EDGE 1: SLAVE latches data on [DAT_I()].MASTER negates [STB_I] and [CYC_I] to indicate the end of the cycle.SLAVE negates [ACK_O[ in response to negated [STB_I]. Block Read and Write cycle XE "Block Read and Write cycle" Block Read and Block Write cycle allows read/write in every clock cycle. The protocol is the same for the single Cycle with the difference that the master should keep the CYC_I and STB_I signals always to “1” during the block cycle.DescriptionSpecificationGeneral description:8-bit Wishbone SLAVESupported cycles:SLAVE, READ/WRITESLAVE, BLOCK READ/WRITEData port, size: CITATION Wis02 \l 1033 (1)Data port, granularity:Data port, maximum operand size:Data transfer ordering:Data transfer sequencing:8-bit8-bit8-bitlittle endianUndefinedClock frequency constraints:40M HzSupported signal list and cross referenceto equivalent WISHBONE signals:Signal NameWISHBONE Equiv.ACK_OACK_OADR_I(3..0)ADR_I()CLK_ICLK_ICYC_ICYC_IDAT_I(7..0)DAT_I()DAT_O(7..0)DAT_O()RST_IRST_ISTB_ISTB_IWE_IWE_ITable SEQ Table \* ARABIC 12. WISHBONE DATASHEET for the SCA_ADC XE "ADC" ADC XE "ADC" OperationsHW reset XE "HW reset" A hardware reset of the SCA_ADC XE "ADC" registers is performed forcing to 1 the WB_RST pin. As this reset is used also to reset the bangap the WB_RST pin should be forced to “1” no less than 250ns [or 10 clock cycles @ 40 MHz].SW reset XE "SW reset" A software reset of the SCA_ADC XE "ADC" is performed when a “1” is written into the bit 7 of the Control Register CREG XE "CREG" [CREG<7>].Wake up XE "Wake up" When the ADC XE "ADC" is in the “power save” state and in order to start a calibration or a conversion it is needed to write a “1” into the bit 5 of the Control Register CREG XE "CREG" [CREG<5> -> wake_up] or write a “0” into the bit 3 of the Control Register CREG [CREG<3> -> sleep].Calibration XE "Calibration" A calibration is performed when a “1” is written into the bit 5 of the Control Register CREG XE "CREG" [CREG<5>] and only if the ADC XE "ADC" is on “ready” state [SREG XE "SREG" <7> = “1”].Set input channel XE "Set input channel" The user should select which input channel the ADC XE "ADC" must use. For doing that is enough to write in the Input Channel Register [ICREG XE "ICREG" ] the address of corresponding input channel according with the table below.ICREG XE "ICREG" <5:0>NameICREG XE "ICREG" <5:0>Name000000InputChannel_1010000InputChannel_17000001InputChannel_2010001InputChannel_18000010InputChannel_3010010InputChannel_19000011InputChannel_4010011InputChannel_20000100InputChannel_5010100InputChannel_21000101InputChannel_6010101InputChannel_22000110InputChannel_7010110InputChannel_23000111InputChannel_8010111InputChannel_24001000InputChannel_9011000InputChannel_25001001InputChannel_10011001InputChannel_26001010InputChannel_11011010InputChannel_27001011InputChannel_12011011InputChannel_28001100InputChannel_13011100InputChannel_29001101InputChannel_14011101InputChannel_30001110InputChannel_15011110InputChannel_31001111InputChannel_16011111InputChannel_32100000GND100001BandGap voltage100010Half_VDD100011GNDTable SEQ Table \* ARABIC 13. Input channel addresses.Conversion/acquisition XE "Conversion/acquisition" A conversion is performed when a “1” is written into the bit 4 of the Control Register CREG XE "CREG" [CREG<4>] and only if the ADC XE "ADC" is on “ready” state [SREG XE "SREG" <7> = “1”] and CREG<5> is “0”, this is, no calibration command is pending.Read Result XE "Read Result" When the bit 6 of the Status Register SREG XE "SREG" <6> contains a “1”, the result of the last acquisition can be read: Data<12:8> = DHREG XE "DHREG" <4:0>Data<7:0> = DLREG XE "DLREG" <7:0>SCA_ADC XE "ADC" conversion OperationA conversion cycle of the ADC XE "ADC" can be simply started by setting the proper channel address in the Input Channel Register and setting the conversion bit in the Control Register CREG XE "CREG" <4>. The conversion bit CREG<4> is cleared automatically at the beginning of the conversion. For instance, a conversion on the input channel 5 can be started by writing “00000100” [0x04] into ICREG XE "ICREG" to select the desired input channel and then writing “00010000” [0x10] into the Control Register [CREG].JTAG Channel XE "GBT-SCA" GeneralA simplified JTAG XE "JTAG" master channel is implemented in the GBT XE "GBT" -SCA XE "GBT-SCA" . The JTAG master generates the three signals TCK XE "TCK" , TMS XE "TMS" and TDO XE "TDO" .TCK is the scan chain clock, TMS the mode control bit for the JTAG slave state machines and TDO is the serial data sent to the scan chain. Data is returned on the TDI XE "TDI" line. The transitions on TMS and TDO take place upon the rising edge of TCK. TDI is sampled on the positive edge of TCK. There is no autonomous JTAG controller – TAP state machine –and the protocol must be implemented in software. Each command is composed of 256 bits, which are split into 128 couples of TMS XE "TMS" and TDO XE "TDO" bits. It takes 16 clock cycles to load the command into the port BUFFER XE "BUFFER" as the Wish-Bone bus is 16-bit wide. The control register CRA XE "CRA" contains an ENREAD XE "ENREAD" bit that, if set at 1 via a JTAG XE "JTAG" CMD WRITE CRA command, indicates that the TDI XE "TDI" bit must be sampled and sent back along with the reply packet. Hence, there are two possible replies, one is the normal reply packet to acknowledge the command and the other one contains also the TDI data which is sampled to fill the first128 LSB bits of the same BUFFER. Thus, any JTAG command must be fragmented into frames of 128 couples of 128 bits – (TMS,TDO) – from the SCA to the front end and into frames of 128 bits (TDI) from the front end to the SCA. In other words, a command of any length can be composed into fragments of 128 bits for TDO and TDI and the last fragment must be completed with idle bits. In addition, a RES_OUT XE "RES_OUT" pin (CRA[7]) is available to force an output pin to a continuous reset value.2190750147320BUFFER256-bit(TMS TDO)0BUFFER256-bit(TMS TDO)4003040180340TCKTCK8699507493016-bit WB bus16-bit WB bus4003040198755TMSTMS63817519685012693656921537712652540607060127000129857537465377126520955400304037465TDOTDO377126581915400304081915TDITDI377126590805404114012700RES_OUTRES_OUT3809365279400Figure SEQ Figure \* ARABIC 23 256-bit JTAG XE "JTAG" BUFFER XE "BUFFER" Through the WishBone bus the packets are segmented and transferred via couples of bytes as shown in the top side of the figure below.3771265149860WishBone segmentationJTAG segmentation020000WishBone segmentationJTAG segmentation2839720-34925002127885-34925001400810-3492500623570-3492500BYTE2456180-89408000809625-33528000The JTAG XE "JTAG" packets are segmented with an unlimited number of bytes.Figure SEQ Figure \* ARABIC 24 JTAG XE "JTAG" packetsThe following registers control the operation of each JTAG XE "JTAG" channel:NameFunctionCRA XE "CRA" Control RegisterSRA XE "SRA" Status RegisterFigure SEQ Figure \* ARABIC 25 Registers in JTAG XE "JTAG" busThe JTAG XE "JTAG" Control register CRA XE "CRA" is defined as follows:BitNameFunction1-0SPEEDDenotes the width of the strobe signals on the port00 – 1000ns01 – 500ns10 – 200ns11 – 100ns. Initialised to “00” after power up and reset.4-2 -----Reserved5ENREAD XE "ENREAD" Enable read6FACKW7RES_OUT XE "RES_OUT" Reset Output Pin: default @ 0Figure SEQ Figure \* ARABIC 26 Control Register in JTAG XE "JTAG" channelThe JTAG XE "JTAG" Status register SRA XE "SRA" is defined as follows:BitNameFunction1-0 -----Reserved2SUCCCommand succeded4-3 -----Reserved5INVCOM XE "INVCOM" Invalid Command6NOACK XE "NOACK" No acknowledge7GE XE "GE" Global errorFigure SEQ Figure \* ARABIC 27 Staus Register in JTAG XE "JTAG" channelJTAG XE "JTAG" commandThe following table summarizes all the commands accepted by the JTAG XE "JTAG" channel. Below CH# is 0x60 except for “SCA Reset XE "SCA Reset" ”.ActionCMD[Hex]Command Packet FormatJTAG XE "JTAG" CMD WRITE CRA XE "CRA" 0xF0C: CH# + TR# + CMD + DWR: CH# + TR# + ACK + SRA XE "SRA" JTAG XE "JTAG" CMD READ CRA XE "CRA" 0xF1C: CH# + TR# + CMDR: CH# + TR# + ACK + CRA XE "CRA" JTAG XE "JTAG" CMD READ SRA XE "SRA" 0xF2C: CH# + TR# + CMDR: CH# + TR# + ACK + SRA XE "SRA" JTAG XE "JTAG" CMD RW0xF3C: CH# + TR# + CMD + (TMS XE "TMS" ,TDO XE "TDO" )[255:0]R: CH# + TR# + ACK + TDI XE "TDI" [127:0] if ENREAD XE "ENREAD" =1R: CH# + TR# + ACK + CRA XE "CRA" if ENREAD XE "ENREAD" =0JTAG XE "JTAG" CMD RESET0xFFC: CH# + TR# + CMDR: noneSCA Reset XE "SCA Reset" 0xAAC: CH#=0xAA + TR# + CMD=0xAA R: noneReset the NC and all the front-end portsFigure SEQ Figure \* ARABIC 28 Commands in JTAG XE "JTAG" portMemory Channel XE "GBT-SCA" GeneralThe Memory Data bus implemented on the GBT XE "GBT" -SCA XE "GBT-SCA" can address a 64KB memory XE "memory" through a 16-bit address and16-bit wide data interface. It can perform single and multiple byte read-write operations as on a normal byte-wide memory device. The operations foreseen are:single byte read-write to addressmultiple (up to 2K) bytes read-write to address with automatically incremented addressesread-modify-write single byte to address with mask Several registers control the operation of the memory XE "memory" bus channel.NameCommentCRA XE "CRA" Control register ASRA XE "SRA" Status register AFigure SEQ Figure \* ARABIC 29 Registers in memory XE "memory" bus channelTo simplify the design of simple peripheral devices connected to the GBT XE "GBT" -SCA XE "GBT-SCA" memory XE "memory" channel, the GBT-SCA provides pre-decoding of up to two memory ranges defined in the window registers.Memory Bus Control registersThe Control register is defined as follows:BitNameFunction--------- ReservedFigure SEQ Figure \* ARABIC 30 Control register A in memory XE "memory" channelMemory Bus Status RegistersBitNameFunction0-4------Reserved5INVCOM XE "INVCOM" Invalid command received. Cleared by channel reset.6INVADDInvalid address. One command with a memory XE "memory" write operation was received with an address outside both window ranges. Cleared by channel reset.7GE XE "GE" Global error. Logical OR of all error conditions in the interfaceFigure SEQ Figure \* ARABIC 31 Status register in memory XE "memory" channelMemory Bus CommandsThe commands used for operating the Memory Bus interface are defined in this paragraph. Below CH# is 0x40 except for “SCA Reset XE "SCA Reset" ”.ActionCMD[Hex]Command Packet FormatMBUS Reset channel0xFFC: CH# + TR# + CMDR: noneWrite control register XE "Write control register" A0x01C: CH# + TR# + CMD + DWR: CH# + TR# + ACK + CRA XE "CRA" Read Control Register XE "Read Control Register" A0x02C: CH# + TR# + CMDR: CH# + TR# + ACK + CRA XE "CRA" Read Status Register XE "Read Status Register" 0x0fC: CH# + TR# + CMDR: CH# + TR# + ACK + SRA XE "SRA" Single 16-bit Word Write to memory XE "memory" 0x10C: CH# + TR# + CMD + AH + AL + DH + DLR: CH# + TR# + ACK + SRA XE "SRA" Single 16-bit Word Read from memory XE "memory" 0x11C: CH# + TR# + CMD + AH + ALR: CH# + TR# + ACK + DH + DLSCA Reset XE “SCA Reset” 0xAAC: CH#=0xAA + TR# + CMD=0xAA R: noneReset the NC and all the front-end portsFigure SEQ Figure \* ARABIC 32 Memory Bus channel CommandsThe Memory address is divided into the two bytes AH and AL, for the high and low part of the address respectively. The block length (max 2 K) is also divided into two bytes, LENH and LENL.In case of corrupted the GBT XE “GBT” -SCA XE “GBT-SCA” signals the error condition through the bit 0 in Status Register A in the Network Controller XE “Network Controller” .Figure SEQ Figure \* ARABIC 33 Memory Bus Command Windowsparallel i/o Channel bus (pia) XE “GBT-SCA” GeneralThe parallel I/O bus channel is an adapter similar to a Motorola PIA XE “PIA” interface, allowing parallel connections with individually programmable direction in groups of 8 bits. Four independent byte PIA adapter channels are available in the GBT XE “GBT” -SCA XE “GBT-SCA” . These PIA ports are selected by default, at power on, over the Memory channel as they share the same 40 output pins. To deselect this mode, and serve the Memory channel, please refer to Network Controller XE “Network Controller” CRA XE “CRA” <0> bit that must be set to 1 via a CRA write command.The 4 PIA XE “PIA” ports also have The following registers control the operation of each PIO channel:NameFunctionGCRGeneral control registerSRStatus RegisterDDRData direction register for PortDREG_IN XE “DREG_IN” Data input registerDREG_OUT XE “DREG_OUT” Data output registerFigure SEQ Figure \* ARABIC 34 Registers in Parallel IO busRegisters in PIA XE “PIA” channelThe functions of the registers are detailed in the following paragraphs.An input strobe (STRIN XE “STRIN” ), active high, is used to latch the PIO port to the DREG_IN XE “DREG_IN” register. The STRIN ping is sampled by the clock and synchronized to avoid metastability. For this reason it is required the STRIN pin being high for at least 25 ns. Thus, at the rising edge of this pin the PIA XE “PIA” port is read out and saved into the DREG_IN, according to the DDREG bits, i.e. only the input pins are updated. The seventh bit of the GCR, EN_STRIN XE “STRIN” , can force the update independently of the STRIN pin. In this case, with EN_STRIN at 1, the DREG_IN XE “DREG_IN” is continuously updated.The STROUT XE “STROUT” pin indicated when the DREG_OUT XE “DREG_OUT” has been updated to the PIA XE “PIA” port.4572001048385PIA 800PIA 89144001204595342900131889503429007473950457200518795STROUT0STROUT457200290195STRINSTRIN3429005187951828800175895PIAGCR, SR, DDRDREG_INDREG_OUT0PIAGCR, SR, DDRDREG_INDREG_OUTGeneral Control Register in PIOThe PIO Control register is defined as follows:BitNameFunction0 - 4 ----- Reserved5ENINTAEnables generation of Interrupt message to GBT XE "GBT" on reception of STRIN XE "STRIN" . The reply will be in the form:<#PORT> + FF + 00 + <DREG_IN XE "DREG_IN" >6 ----- Reserved7EN_STRIN XE "STRIN" Enables the DATA_IN register to be automatically updated with the PIA XE "PIA" port: no STROBE_IN is required. Default @ 0.Figure SEQ Figure \* ARABIC 35 General Control Register in PIO channelStatus Register in PIA XE "PIA" BitNameFunction0INTAn interrupt was generated by a strobe on Port. Cleared by writing a “1” to the CLR bit in GCR.1-4Reserved5INVCOM XE "INVCOM" Invalid command received. Cleared by channel reset. Does not generate a GE XE "GE" bit (see below)6 ----- Reserved7GE XE "GE" Global error. Logical OR of all error conditions in the PIO interfaceFigure SEQ Figure \* ARABIC 36 Status register in PIO channelCommands for PIA XE "PIA" channelThe following commands are defined for the PIO channel. Below CH# is 0x30-0x33 except for “SCA Reset XE "SCA Reset" ”.ActionCMD[Hex]Command Packet FormatWrite General Control Register (GCR)0x01C: CH# + TR# + CMD + DWR: CH# + TR# + ACK + GCRRead General Control Register (GCR)0x02C: CH# + TR# + CMDR: CH# + TR# + ACK + GCRRead Status Register XE "Read Status Register" (SR)0x03C: CH# + TR# + CMDR: CH# + TR# + ACK + SRWrite Data Direction Register (DDR)0x04C: CH# + TR# + CMD + DWR: CH# + TR# + ACK + DDRRead Data Direction Register (DDR)0x05C: CH# + TR# + CMDR: CH# + TR# + ACK + DDRWrite Data Register Out (DREG_OUT XE "DREG_OUT" )0x06C: CH# + TR# + CMD + DWR: CH# + TR# + ACK + DREG_OUT XE "DREG_OUT" Read Data Register Out (DREG_OUT XE "DREG_OUT" )0x07C: CH# + TR# + CMDR: CH# + TR# + ACK + DREG_OUT XE "DREG_OUT" CMD Read/Write PIA XE "PIA" 0x08C: CH# + TR# + CMDR: CH# + TR# + ACK + DREG_IN XE "DREG_IN" PIA XE "PIA" Reset channel0xFFC: CH# + TR# + CMDR: noneSCA Reset XE "SCA Reset" 0xAAC: CH#=0xAA + TR# + CMD=0xAA R: noneReset the NC and all the front-end portsFigure SEQ Figure \* ARABIC 37 Commands for PIO channelDAC Channel XE "GBT-SCA" GeneralDAC XE "DAC" CommandsThe commands used for operating the DAC XE "DAC" interface are defined in this paragraph. It consists of an 8-bit register that can be written or read out. Its value is then converted to the output analog port.Below CH# is 0x80-83 except for “SCA Reset XE "SCA Reset" ”.ActionCMD[Hex]Command Packet FormatDAC XE "DAC" Reset channel0xFFC: CH# + TR# + CMDR: noneWrite control register XE "Write control register" 0xF0C: CH# + TR# + CMD + DWR: CH# + TR# + ACK + CRRead Control Register XE "Read Control Register" 0xF1C: CH# + TR# + CMDR: CH# + TR# + ACK + CRRead Status Register XE "Read Status Register" 0xF2C: CH# + TR# + CMDR: CH# + TR# + ACK + SRWrite DAC XE "DAC" register0xF3C: CH# + TR# + CMD + DATAR: CH# + TR# + ACK + SRRead DAC XE "DAC" register0xF4C: CH# + TR# + CMDR: CH# + TR# + ACK + DRSCA Reset XE "SCA Reset" 0xAAC: CH#=0xAA + TR# + CMD=0xAA R: noneReset the NC and all the front-end portsFigure SEQ Figure \* ARABIC 38 DAC XE "DAC" channel CommandsNB. Here the DAC XE "DAC" Reset and SCA Reset XE "SCA Reset" commands force the ADC XE "ADC" internal channel to be reset for 20 clock cycles.SPI Channel XE "GBT-SCA" GeneralThe Serial Peripheral Interface (SPI XE "SPI" ) bus is a synchronous byte-oriented serial data link standard that operates in full duplex mode. Devices communicate only in master-to-slave mode where the master device initiates the data frame. The SPI master generates the three signals Serial Clock (SCK XE "SCK" ), Slave Select (SSb XE "SSb" ) and Master Output Slave Input (MOSI XE "MOSI" ).SCK is the clock, SSb the mode control bit for the SPI slave state machines and MOSI is the serial data sent to the port. Data is returned on the Master Input Slave Output (MISO XE "MISO" ) line. The transitions on all the signals take place on the positive edge of SCK. Each command can be composed of 8/16/32 MOSI XE "MOSI" bits. It takes 1 to 2 clock cycles to load the command into the port BUFFER XE "BUFFER" - 32 bytes - as the Wish-Bone bus is 16-bit wide. The control register CRA XE "CRA" contains an ENREAD XE "ENREAD" bit that, if set at 1 via a SPI XE "SPI" CMD WRITE CRA command, indicates that the MISO XE "MISO" bit must be sent back along with the reply packet. Hence, there are two possible replies, one is the normal reply packet to acknowledge the command and the other one contains also the MISO data which is sampled to fill the same BUFFER. Thus, any SPI command must be fragmented into frames of 8/16/32 MOSI bits from the SCA, plus the 3 common bytes CH#, TR#, CMD, to the front end and into frames of 8/16/32 MISO bits from the front end to the SCA. In other words, a command of any length can be composed into fragments for MOSI and MISO and the last fragment must be completed with idle bits.100901569850MASTERSPDAT8-256-bit MOSI16-bit WB busMOSISSbSCKMISOSLAVESPDAT8-256-bit MISO00MASTERSPDAT8-256-bit MOSI16-bit WB busMOSISSbSCKMISOSLAVESPDAT8-256-bit MISOFigure SEQ Figure \* ARABIC 39 32-bit SPI XE "SPI" SPDAT bufferThe following registers control the operation of each SPI XE "SPI" channel:NameFunctionSPCRControl RegisterSPSRStatus RegisterSPDAT32-byte RegisterFigure SEQ Figure \* ARABIC 40 Registers in SPI XE "SPI" busThe SPI XE "SPI" Control register is defined as follows:BitNameFunction1-0SPEEDDenotes the width of the strobe signals on the port00 – 1000ns01 – 500ns10 – 200ns11 – 100ns. Initialised to “00” after power up and reset.2CPHAFixed to 03CPOLFixed to 14MSTR5DWOM6SPE7ENREAD XE "ENREAD" Enable readFigure SEQ Figure \* ARABIC 41 Control Register in SPI XE "SPI" channelThe SPI XE "SPI" Status register is defined as follows:BitNameFunction0INVCOM XE "INVCOM" Invalid Command1NOACK XE "NOACK" No acknowledge2GE XE "GE" Global Error3-----Reserved4MODF5-----Reserved6WCOL7SPIFFigure SEQ Figure \* ARABIC 42 Staus Register in SPI XE "SPI" channelSPI XE "SPI" commandThe following table summarizes all the commands accepted by the SPI XE "SPI" channel. Below CH# is 0x02 except for “SCA Reset XE "SCA Reset" ”.ActionCMD[Hex]Command Packet FormatSPI XE "SPI" CMD WRITE SPCR0xF0C: CH# + TR# + CMD + DWR: CH# + TR# + ACK + SRA XE "SRA" SPI XE "SPI" CMD READ SPCR0xF1C: CH# + TR# + CMDR: CH# + TR# + ACK + CRA XE "CRA" SPI XE "SPI" CMD READ SPSR0xF2C: CH# + TR# + CMDR: CH# + TR# + ACK + SRA XE "SRA" SPI XE "SPI" CMD RW 1 byte0xF3C: CH# + TR# + CMD + DW (MOSI XE "MOSI" )R:CH# + TR# + ACK + DR (MISO XE "MISO" )SPI XE "SPI" CMD RW 8 bytes0xF4C: CH# + TR# + CMD + 8*DW (MOSI XE "MOSI" )R:CH# + TR# + ACK + DR (MISO XE "MISO" ) if ENREAD XE "ENREAD" =0R:CH# + TR# + ACK + 8*DR (MISO XE "MISO" ) if ENREAD XE "ENREAD" =1SPI XE "SPI" CMD RW 32 bytes0xF5C: CH# + TR# + CMD + 32*DW (MOSI XE "MOSI" ) R:CH# + TR# + ACK + DR (MISO XE "MISO" ) if ENREAD XE "ENREAD" =0R:CH# + TR# + ACK + 32*DR (MISO XE "MISO" ) if ENREAD XE "ENREAD" =1SPI XE "SPI" CMD RESET0xFFC: CH# + TR# + CMDR: noneSCA Reset XE "SCA Reset" 0xAAC: CH#=0xAA + TR# + CMD=0xAA R: noneReset the NC and all the front-end portsFigure SEQ Figure \* ARABIC 43 Commands in SPI XE "SPI" portSPI XE "SPI" TimingFigure SEQ Figure \* ARABIC 44 SPI Timing WindowsinterruptsFour asynchronous interrupts XE "interrupts" , active low, are handled. The 4 channels cannot be addressed but they can reply.These interrupts XE "interrupts" are polled via the Network Controller XE "Network Controller" that can provide dedicated packets backwards to the GBT XE "GBT" . The interrupts packets are handled like the other reply packets coming from the other ports and hence there is no priority on the ports.The 0xFF transaction IDs are Reserved for the External and PIA XE "PIA" interrupts XE "interrupts" so cannot be used as normal TR#NameActiveCoded ChannelReplyInterrupt 0Low0xFC0x FC-FF-00-FCInterrupt 1Low0xFD0x FD-FF-0-0FDInterrupt 2Low0xFE0x FE-FF-00-FEInterrupt 3Low0xFF0x FF-FF-00-FFFigure SEQ Figure \* ARABIC 45 Interrupts encodingPINOUT – 150 pinsLeft SidePIN NameNotesBottom SidePIN NameNotesRight SidePIN NameNotesTop SidePIN NameNotes1Pery VDDPWRSDA_o<15>I2C-IOMEM_PIA_o<39>Shared-IOADC<31>Analog-I2Pery GNDGNDSDA_o<14>I2C-IOMEM_PIA_o<38>Shared-IOADC<30>Analog-I3Dig VDDPWRSDA_o<13>I2C-IOMEM_PIA_o<37>Shared-IOADC<29>Analog-I4Dig GNDGNDSDA_o<12>I2C-IOMEM_PIA_o<36>Shared-IOADC<28>Analog-I5Ana VDDPWRSDA_o<11>I2C-IOMEM_PIA_o<35>Shared-IOADC<27>Analog-I6Ana GNDGNDSDA_o<10>I2C-IOMEM_PIA_o<34>Shared-IOADC<26>Analog-I7Link_clk_0+ELINK-ISDA_o<9>I2C-IOMEM_PIA_o<33>Shared-IOADC<25>Analog-I8Link_clk_0-ELINK-ISDA_o<8>I2C-IOMEM_PIA_o<32>Shared-IOADC<24>Analog-I9Rx_sd_0+ELINK-ISDA_o<7>I2C-IOMEM_PIA_o<31>Shared-IOADC<23>Analog-I0Rx_sd_0-ELINK-ISDA_o<6>I2C-IOMEM_PIA_o<30>Shared-IOADC<22>Analog-I11Tx_sd_0+ELINK-OSDA_o<5>I2C-IOMEM_PIA_o<29>Shared-IOADC<21>Analog-I12Tx_sd_0-ELINK-OSDA_o<4>I2C-IOMEM_PIA_o<28>Shared-IOADC<20>Analog-I13Link_clk_1+ELINK-ISDA_o<3>I2C-IOMEM_PIA_o<27>Shared-IOADC<19>Analog-I14Link_clk_1-ELINK-ISDA_o<2>I2C-IOMEM_PIA_o<26>Shared-IOADC<18>Analog-I15Rx_sd_1+ELINK-ISDA_o<1>I2C-IOMEM_PIA_o<25>Shared-IOADC<17>Analog-I16Rx_sd_1-ELINK-ISDA_o<0>I2C-IOMEM_PIA_o<24>Shared-IOADC<16>Analog-I17Tx_sd_1+ELINK-OMISOSPI-IMEM_PIA_o<23>Shared-IOADC<15>Analog-I18Tx_sd_1-ELINK-OMOSISPI-OMEM_PIA_o<22>Shared-IOADC<14>Analog-I19SCL_o<15>I2C-OSCKSPI-OMEM_PIA_o<21>Shared-IOADC<13>Analog-I20SCL_o<14>I2C-OSSbSPI-OMEM_PIA_o<20>Shared-IOADC<12>Analog-I21SCL_o<13>I2C-OMEM_PIA_o<13>Shared-IOMEM_PIA_o<19>Shared-IOADC<11>Analog-I22SCL_o<12>I2C-OMEM_PIA_o<12>Shared-IOMEM_PIA_o<18>Shared-IOADC<10>Analog-I23SCL_o<11>I2C-OMEM_PIA_o<11>Shared-IOMEM_PIA_o<17>Shared-IOADC<9>Analog-I24SCL_o<10>I2C-OMEM_PIA_o<10>Shared-IOMEM_PIA_o<16>Shared-IOADC<8>Analog-I25SCL_o<9>I2C-OMEM_PIA_o<9>Shared-IOMEM_PIA_o<15>Shared-IOADC<7>Analog-I26SCL_o<8>I2C-OMEM_PIA_o<8>Shared-IOMEM_PIA_o<14>Shared-IOADC<6>Analog-I27SCL_o<7>I2C-OMEM_PIA_o<7>Shared-IOTDIJTAG-IADC<5>Analog-I28SCL_o<6>I2C-OMEM_PIA_o<6>Shared-IOTMSJTAG-IADC<4>Analog-I29SCL_o<5>I2C-OMEM_PIA_o<5>Shared-IOTCKJTAG-IADC<3>Analog-I30SCL_o<4>I2C-OMEM_PIA_o<4>Shared-IOTDOJTAG-OADC<2>Analog-I31SCL_o<3>I2C-OMEM_PIA_o<3>Shared-IORES_OUTJTAG-OADC<1>Analog-I32SCL_o<2>I2C-OMEM_PIA_o<2>Shared-IOEth-SelOutput InfoADC<0>Analog-I33SCL_o<1>I2C-OMEM_PIA_o<1>Shared-IOAna VDDPWRDAC-0Analog-O34SCL_o<0>I2C-OMEM_PIA_o<0>Shared-IOAna GNDGNDDAC-1Analog-O35Int0Interrupt-IReset_inRESET-IDig VDDPWRDAC-2Analog-O36Int1Interrupt-IExt_Reset_Out XE "Reset_Out" RESET-ODig GNDGNDDAC-3Analog-O37Int2Interrupt-IADCADCPery VDDPWR38Int3Interrupt-IADCADCPery GNDGNDTable SEQ Table \* ARABIC 14. GBT-SCA pinout tableINDEXIndex of Paragraphs TOC \o "1-3" 1.Document History PAGEREF _Toc183587643 \h 22.General PAGEREF _Toc183587644 \h 32.1.Overview of the GBT System PAGEREF _Toc183587645 \h 32.2.Overview of the GBT-SCA Architecture PAGEREF _Toc183587646 \h 42.3.Radiation tolerance features PAGEREF _Toc183587647 \h 83.SCA PACKET description PAGEREF _Toc183587648 \h 93.1.The protocol PAGEREF _Toc183587649 \h 93.2.PAYLOAD Format PAGEREF _Toc183587650 \h 104.ChannelS IN GBT-SCA PAGEREF _Toc183587651 \h 114.1.General PAGEREF _Toc183587652 \h 114.2.Allocations of channels in the GBT-SCA PAGEREF _Toc183587653 \h 114.3.GBT-SCA controller PAGEREF _Toc183587654 \h 125.i2c channel PAGEREF _Toc183587655 \h 165.1.General PAGEREF _Toc183587656 \h 165.1.2.I2C Control registers PAGEREF _Toc183587657 \h 165.1.3.Logical mask register PAGEREF _Toc183587658 \h 165.1.4.I2C Status Registers PAGEREF _Toc183587659 \h 175.1.5.I2C Commands PAGEREF _Toc183587660 \h 186.ADC Channel PAGEREF _Toc183587661 \h 206.1.General PAGEREF _Toc183587662 \h 206.1.1.ADC Commands PAGEREF _Toc183587663 \h 206.1.2.ADC Blocks PAGEREF _Toc183587664 \h 216.1.1.SCA_ADC Internal Registers PAGEREF _Toc183587665 \h 226.1.2.Supported cycles PAGEREF _Toc183587666 \h 257.JTAG Channel PAGEREF _Toc183587667 \h 287.1.General PAGEREF _Toc183587668 \h 287.1.1.JTAG command PAGEREF _Toc183587669 \h 308.Memory Channel PAGEREF _Toc183587670 \h 318.1.General PAGEREF _Toc183587671 \h 318.1.1.Memory Bus Control registers PAGEREF _Toc183587672 \h 318.1.2.Memory Bus Status Registers PAGEREF _Toc183587673 \h 318.1.3.Memory Bus Commands PAGEREF _Toc183587674 \h 329.parallel i/o Channel bus (pia) PAGEREF _Toc183587675 \h 339.1.General PAGEREF _Toc183587676 \h 339.1.1.Registers in PIA channel PAGEREF _Toc183587677 \h 339.1.mands for PIA channel PAGEREF _Toc183587678 \h 3510.DAC Channel PAGEREF _Toc183587679 \h 3610.1.General PAGEREF _Toc183587680 \h 3610.1.1.DAC Commands PAGEREF _Toc183587681 \h 3611.SPI Channel PAGEREF _Toc183587682 \h 3711.1.General PAGEREF _Toc183587683 \h 3711.1.1.SPI command PAGEREF _Toc183587684 \h 3911.1.2.SPI Timing PAGEREF _Toc183587685 \h 3912.interrupts PAGEREF _Toc183587686 \h 4013.PINOUT – 150 pins PAGEREF _Toc183587687 \h 4114.INDEX PAGEREF _Toc183587688 \h 4314.1.Index of Paragraphs PAGEREF _Toc183587689 \h 4314.1.Index of Terms PAGEREF _Toc183587690 \h 4514.2.Index of Figures PAGEREF _Toc183587691 \h 4614.3.Index of Tables PAGEREF _Toc183587692 \h 46Index of Terms INDEX \c "2" ADC, 6, 11, 13, 20, 21, 22, 23, 24, 26, 27, 36BGHREG, 22, 23, 24BGLREG, 22, 23, 24Block Read and Write cycle, 26BUFFER, 28, 37Calibration, 21, 22, 23, 26CALREG, 22, 23, 24Channel Number, 11Conversion/acquisition, 27CRA, 12, 14, 16, 17, 28, 29, 30, 31, 32, 33, 37, 39CRC, 9, 12, 14CRD, 12, 14CRE, 12, 14, 15CREG, 22, 23, 26, 27DAC, 6, 11, 13, 36DHREG, 22, 23, 27DLREG, 22, 23, 27DREG_IN, 33, 34, 35DREG_OUT, 33, 35ENREAD, 28, 29, 30, 37, 38, 39Err CHN, 14Err ERR, 14Err TR, 14GBT, 1, 3, 4, 5, 6, 7, 9, 11, 12, 14, 17, 28, 31, 32, 33, 34, 40GBT-SCA, 1, 3, 4, 5, 6, 7, 11, 12, 14, 20, 28, 31, 32, 33, 36, 37GE, 14, 17, 29, 31, 34, 38GmCal, 22, 24HW reset, 26I2C, 5, 6, 10, 11, 13, 16, 17, 18, 19ICREG, 22, 23, 27Interrupt Channel, 11interrupts, 6, 11, 40INVCOM, 17, 29, 31, 34, 38JTAG, 5, 10, 11, 13, 28, 29, 30memory, 6, 31, 32Memory Channel, 5, 11MISO, 37, 39MOSI, 37, 39MSK, 16Network Controller, 5, 6, 8, 11, 12, 15, 32, 33, 40NOACK, 17, 29, 38PIA, 5, 6, 11, 12, 13, 33, 34, 35, 40Read Control Register, 20, 32, 36Read Result, 27Read Status Register, 20, 32, 35, 36RES_OUT, 28, 29Reset Tree, 6Reset_Out, 12, 41SCA Reset, 11, 14, 15, 18, 19, 20, 30, 32, 35, 36, 39SCK, 37Set input channel, 26SINGLE READ Cycle, 25SINGLE WRITE Cycle, 25SPI, 6, 10, 11, 13, 37, 38, 39SRA, 12, 15, 16, 29, 30, 31, 32, 39SRB, 12, 15, 16SREG, 22, 23, 24, 26, 27SSb, 37STRIN, 33, 34STROUT, 33SW reset, 26TCK, 28TDI, 28, 30TDO, 28, 30TMS, 28, 30TREG, 22, 24Wake up, 26Write control register, 20, 32, 36Index of Figures TOC \c "Figure" Figure 1 Control module, simplified view PAGEREF _Toc183587693 \h 4Figure 2 E-port Redundancy PAGEREF _Toc183587694 \h 5Figure 3: block diagram of the GBT-SCA: PAGEREF _Toc183587695 \h 7Figure 4: Logic Reset Tree of the GBT-SCA PAGEREF _Toc183587696 \h 7Figure 5: MAC to Network Controller interface PAGEREF _Toc183587697 \h 8Figure 6: SCA Packet communication system PAGEREF _Toc183587698 \h 9Figure 7: SCA-to-Port Command Packet example PAGEREF _Toc183587699 \h 10Figure 8: Port-to-SCA Reply Packet example PAGEREF _Toc183587700 \h 10Figure 9: Channel number allocation PAGEREF _Toc183587701 \h 11Figure 10: Control and Status registers in GBT-SCA Controller PAGEREF _Toc183587702 \h 12Figure 11 Network Controller control register A PAGEREF _Toc183587703 \h 12Figure 12 Control register B-C-D-E in Network Controller PAGEREF _Toc183587704 \h 13Figure 13 Node Controller status register A PAGEREF _Toc183587705 \h 14Figure 14 Commands for the Network Controller PAGEREF _Toc183587706 \h 15Figure 15 Control and Status registers in I2C channel PAGEREF _Toc183587707 \h 16Figure 16 Control register A in I2C interface PAGEREF _Toc183587708 \h 16Figure 17 Status register A in I2C interface PAGEREF _Toc183587709 \h 17Figure 18 Commands for I2C channel PAGEREF _Toc183587710 \h 19Figure 19 ADC channel Commands PAGEREF _Toc183587711 \h 20Figure 20 SCA_ADC architecture PAGEREF _Toc183587712 \h 21Figure 23 256-bit JTAG BUFFER PAGEREF _Toc183587713 \h 28Figure 24 JTAG packets PAGEREF _Toc183587714 \h 28Figure 25 Registers in JTAG bus PAGEREF _Toc183587715 \h 29Figure 26 Control Register in JTAG channel PAGEREF _Toc183587716 \h 29Figure 27 Staus Register in JTAG channel PAGEREF _Toc183587717 \h 29Figure 28 Commands in JTAG port PAGEREF _Toc183587718 \h 30Figure 29 Registers in memory bus channel PAGEREF _Toc183587719 \h 31Figure 30 Control register A in memory channel PAGEREF _Toc183587720 \h 31Figure 31 Status register in memory channel PAGEREF _Toc183587721 \h 31Figure 32 Memory Bus channel Commands PAGEREF _Toc183587722 \h 32Figure 33 Memory Bus Command Windows PAGEREF _Toc183587723 \h 32Figure 34 Registers in Parallel IO bus PAGEREF _Toc183587724 \h 33Figure 35 General Control Register in PIO channel PAGEREF _Toc183587725 \h 34Figure 36 Status register in PIO channel PAGEREF _Toc183587726 \h 34Figure 37 Commands for PIO channel PAGEREF _Toc183587727 \h 35Figure 38 DAC channel Commands PAGEREF _Toc183587728 \h 36Figure 39 32-bit SPI SPDAT buffer PAGEREF _Toc183587729 \h 37Figure 40 Registers in SPI bus PAGEREF _Toc183587730 \h 37Figure 41 Control Register in SPI channel PAGEREF _Toc183587731 \h 38Figure 42 Staus Register in SPI channel PAGEREF _Toc183587732 \h 38Figure 43 Commands in SPI port PAGEREF _Toc183587733 \h 39Figure 44 SPI Timing Windows PAGEREF _Toc183587734 \h 39Figure 45 Interrupts encoding PAGEREF _Toc183587735 \h 40Index of Tables TOC \c "Table" Table 1. The SCA_ADC register file PAGEREF _Toc178412184 \h 22Table 2. Bit assignment of Status register (SREG). PAGEREF _Toc178412185 \h 22Table 3. Bit assignment of Control register (CREG). PAGEREF _Toc178412186 \h 23Table 4. Bit assignment of Input channel register (ICREG). PAGEREF _Toc178412187 \h 23Table 5. Bit assignment of Data High and Low registers (DHREG/DLREG). PAGEREF _Toc178412188 \h 23Table 6. Bit assignment of Calibration register (CALREG). PAGEREF _Toc178412189 \h 23Table 7. Bit assignment of BandgapCal High and Low registers (BGHREG/BGLREG). PAGEREF _Toc178412190 \h 24Table 8. Bit assignment of GmCal High and Low registers (GMHREG/GMLREG). PAGEREF _Toc178412191 \h 24Table 9. Bit assignment of IdCal High and Low registers (IDHREG/IDLREG). PAGEREF _Toc178412192 \h 24Table 10. Bit assignment of Test register (TREG). PAGEREF _Toc178412193 \h 24Table 11. Wishbone signals PAGEREF _Toc178412194 \h 25Table 12. WISHBONE DATASHEET for the SCA_ADC PAGEREF _Toc178412195 \h 26Table 13. Input channel addresses. PAGEREF _Toc178412196 \h 27Table 14. GBT-SCA pinout table PAGEREF _Toc178412197 \h 41 ................
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