Pierce osicaillator, What does STOP is for,



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Jordan University of Science and Technology

Department of Computer Engineering

CpE 252: Computer Organization & Design

First Exam - 2004/2005 second semester

|Student Name | |Section No. | |

|Q. No. |Q1 |Q2 |Q3 |Q4 |Q5 |Total |

|Points |5 |5 |5 |5 |5 |25 |

|Mark | | | | | | |

|Instructions: |

| |

|Keep your books and notes closed and at a distance |

|Turn off your cell phone and don’t use it as a calculator |

|Communicate only with the professor or the proctor |

|Don’t ask about the time, will announce when it is ½ and ¾ … |

|Use non red colored pen (no pencil) |

|Be neat, precise, brief and up to the point |

|Answer all questions in the dedicated space |

|Time allowed is 60 minutes |

|Instructors will answer your questions in the first 30 minutes only |

|Stop writing and submit the booklet upon hearing “pens down” |

|Keep your school ID on the desk for the proctors to verify your identity |

| |

|Er. Shadi Ayoub, Dr. Lo’ai Tawalbeh and Dr. Taisir Eldos (Coordinator) |

1. Connect the components in the following figure to achieve the implementation of the RTL statements shown below. Note that R1 is a 4-bit counter with parallel Load (LD) and Increment (INR) controls. R2 is a 4-bit register with parallel Load. P, Q and W are control signals

If (P = 1 OR Q = 0) then R1 ( R1 + 1

else if (W = 1) then R2 ( R1 + R2

END

2. Mark the most appropriate answer for each of the following questions:

a. Assume the initial value of a register is 100110102. If we apply an Arithmetic Shift Right operation followed by a Circular Shift Left operation to this register, then the final contents of this register will be:

x. 100110102 y. 111001102 z. 100110112 w. No change

b. A computer system with 6 registers 32-bit each, and a 2048×16 memory unit. These components are connected to a common bus constructed using multiplexers. What is the number and the size of these multiplexers?

x. 16 8x1 y. 32 4x1 z. 32 8x1 w. 32 16x1

c. If the size of AR and PC of the "Basic Computer" is reduced by 1 bit, then which of the following is correct:

x. Increase the complexity of the bus

y. Nothing will be changed

z. Increase the size of the memory

w. Possibility for adding more memory-reference instructions

d. If it takes 2 cycles to fetch, 1 cycle to decode, and up to 3 cycles to execute register reference instructions, then the smallest size of the sequence counter and its decoder will be:

x. 3 , 8 y. 4 , 8 z. 4 , 16 w. 4 , 32

e. To stop the sequence counter of the “Basic Computer” from counting, we use the condition:

x. RT0 y. D7′I′T3 z. D7I′T3B0 w. None

3. For parts a. and b. below, assume that AC = C38916, the memory word stored at address 02216 is 003616, and the memory word stored at address 003616 is FD5916. Refer to the handouts to answer the following independent questions:

a. What would be the value stored in AC and E after executing the instruction

00010000000101102 ?

b. What would be the value stored in AC and E after executing the instruction

10010000001001002 ?

4. Design a 1-bit Logic Shift Unit (LSU) that performs the following functions and show how to use it as a module to construct a 4-bit LSU (you can use the back of this page to draw)

Operation # Operations Description

1 AND F = A and B

2 OR F = A or B

3 NOT F = A’

4 PASS F = A

5 LSL F = Logic Shift Left A

6 LSR F = Logic Shift Right A

5. The following two instructions are not implemented in the” Basic Computer” we have studied so far. Show a sequence of instructions that implement each of them

STE (means set the flip-flop E)

DEC (means decrement Accumulator)

-----------------------

0

Cin

LD

LD

INR

4-bit

4-bit

4-bit

4-bit

Clock

4-bit Adder

R2

R1

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