Common Combinational Logic Circuits - Auburn University
Common Combinational Logic Circuits
? Adders
? Subtraction typically via 2s complement addition
? Multiplexers
? N control signals select 1 of up to 2N inputs as output
? Demultiplexers
? N control signals select input to go to 1 of up to 2N outputs
? Decoders
? N inputs produce M outputs (typically M > N)
? Encoders
? N inputs produce M outputs (typically N > M)
? Converter (same as decoder or encoder)
? N inputs produce M outputs (typically N = M)
C. E. Stroud
Combinational Logic Circuits (10/12)
1
More Common Circuits
? Comparators
? Compare two N-bit binary values
? Equal-to or Not-equal-to
? Easiest to design
? Greater-than, Less-than, Greater-than-or-equal-to, etc.
? Require adders
? Parity check/generate circuit
? Calculates even or odd parity over N bits of data ? Checks for good/bad parity (parity errors) on
incoming data
C. E. Stroud
Combinational Logic Circuits (10/12)
2
Adders
? Consider ith column addition of 2 binary numbers (A and B)
? Ai + Bi + Cini = Couti + Sumi
? Derive truth table
? Populate K-maps
? Obtain minimized SOPs
? Draw logic diagram
? Optimize with P&Ts
Truth Table
A B C Co S 000 0 0 001 0 1 010 0 1 011 1 0 100 0 1 101 1 0 110 1 0 111 1 1
BC A 00 01 11 10
00 1 0 1 11 0 1 0
S=A'B'C+A'BC' +AB'C'+ABC =A'(BC)+A(BC) =ABC
BC A 00 01 11 10
00 0 1 0 10 1 1 1
Co=BC+AC+AB
C. E. Stroud
Combinational Logic Circuits (10/12)
3
Adders
A
B
S=ABC
C
Co=BC+ AC+AB
A
Taking advantage of common B product terms between S and Co C we see that we can use the XOR gate for AB to reduce the gate
count
BC A 00 01 11 10
00 0 1 0 10 1 1 1
Co=A'BC+AB'C+AB =C(A'B+AB')+AB =C(AB)+AB
S=ABC
Co=BC+ AC+AB
C. E. Stroud
Combinational Logic Circuits (10/12)
4
Adders
referred to as a full adder
A
B
S=ABC
C
Co=BC+ AC+AB
now we can build an N-bit adder from N full adders
Cin
A0
AS
S0
B0
B FA
C Co
we can let a block represent the full adder
A
B full S adder
Cin Cout
A1
AS
S1
B1
B FA
C Co
AN-1
AS
BN-1
B FA
C Co
SN-1 Cout
C. E. Stroud
Combinational Logic Circuits (10/12)
5
Subtractors
Build an N-bit subtractor from an N-bit adder using 2's complement
?Recall the 2's complement A0
transformation for a
B0
negative number:
1) invert
A1
2) then add 1
B1
here we use Cin
to add a 1
?Therefore, S=A-B
AN-1
?Note that this includes
BN-1
a sign bit (SN-1)
Cin=1
AS
B FA
C Co
AS
B FA
C Co
AS
B FA
C Co
C. E. Stroud
Combinational Logic Circuits (10/12)
S0 S1
SN-1 Cout
6
Multiplexers
? N control signals select 1 of up to 2N inputs as output
? Sometimes called selectors ? We looked at a 2-to-1 MUX
A
S B
G=4 GIO=11 Gdel=3
C. E. Stroud
A
Z
0Z B
1
Z = AS' + BS S if S=0, then Z=A else if S=1, then Z=B
Combinational Logic Circuits (10/12)
In0
Out In2N-1
N Select Control
7
Short-hand Truth Table
Multiplexers S1 S0 Z
? 4-to-1 MUX
? 4 inputs
? In0-3
? 2 controls
? S1, S0 (LSB)
In0 0 In1 1 In2 2 In3 3
Z
In0
? 1 output
?Z
S1
S1 S0
S0
In1
? Can generated any size MUX
S1
S0
Z = In0 S1' S0' + In1 S1' S0
In2
+ In2 S1 S0' + In3 S1 S0 S0
S1 S0 S0
SOP obtained directly from S1 short-hand Truth Table
S1 In3 S1 S0
0 0 In0 0 1 In1 1 0 In2 1 1 In3
Z
G=7 GIO=25 Gdel=3
C. E. Stroud
Combinational Logic Circuits (10/12)
8
................
................
In order to avoid copyright disputes, this page is only a partial summary.
To fulfill the demand for quickly locating and searching documents.
It is intelligent file search solution for home and business.
Related download
- 45 41 63 63 33 42 super teacher worksheets
- inequalities symbols and vocabulary mt sac
- common combinational logic circuits auburn university
- highlights of prescribing information still s disease novartis
- statistics 8 chapters 7 to 10 sample multiple choice questions
- goals for chapter 7 chapter 7 physics
- chapter 7 linear programming models graphical and computer models dr
- 2 digit compare the numbers using greater than less than
- translating linear inequalities math worksheets 4 kids
- unit 7 test equilibrium relearning weebly