Using Verilog for Testbenches - ETH Z

[Pages:22]Carnegie Mellon

Using Verilog for Testbenches

Design of Digital Circuits 2014 Srdjan Capkun Frank K. G?rkaynak



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Adapted from Digital Design and Computer Architecture, David Money Harris & Sarah L. Harris ?2007 Elsevier

What Will We Learn?

How to simulate your circuit Applying inputs Seeing if the circuit does the correct thing

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How Do You Know That A Circuit Works?

You have written the Verilog code of a circuit

Does it work correctly? Even if the syntax is correct, it might do what you want? What exactly it is that you want anyway?

Trial and error can be costly

You need to `test' your circuit in advance

In modern digital designs, functional verification is the most time consuming design stage.

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The Idea Behind A Testbench

Using a computer simulator to test your circuit

You instantiate your design Supply the circuit with some inputs See what it does Does it return the "correct" outputs?

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Testbenches

HDL code written to test another HDL module, the device under test (dut), also called the unit under test (uut)

Not synthesizeable Types of testbenches:

Simple testbench Self-checking testbench Self-checking testbench with testvectors

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Example

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Write Verilog code to implement the following function in hardware:

y = (b c) + (a b)

Name the module sillyfunction

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Example

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Write Verilog code to implement the following function in hardware:

y = (b c) + (a b)

Name the module sillyfunction

module sillyfunction(input a, b, c, output y);

assign y = ~b & ~c | a & ~b; endmodule

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Simple Testbench

module testbench1(); // Testbench has no inputs, outputs

reg a, b, c;

// Will be assigned in initial block

wire y;

// instantiate device under test sillyfunction dut (.a(a), .b(b), .c(c), .y(y) );d

// apply inputs one at a time

initial begin

// sequential block

a = 0; b = 0; c = 0; #10; // apply inputs, wait 10ns

c = 1; #10;

// apply inputs, wait 10ns

b = 1; c = 0; #10;

// etc .. etc..

c = 1; #10;

a = 1; b = 0; c = 0; #10;

end

endmodule

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