TUTORIAL Task: Solution (VHDL)

TUTORIAL Task:

Implement a simple 2-input logic AND gate, firstly, using VHDL, then with IP integrator. Simulate and test both designs on FPGA development board. Connect inputs to Push Buttons or Switches and observe output on a LED. For pin numbers check either manual or the board itself (written in parenthesis besides each component).

Solution (VHDL)

Double-click Vivado icon on the computer desktop to start the program. Select New Project option from the File menu to start the New Project Wizard.

Figure 1. New Project Wizard 1st Window

Name the project (a directory of the same name is created to store the project files). Do not store projects in folders, which have spaces in either name or the path. Make sure that the Create Project Subdirectory box is checked. Press Next to proceed. Select RTL Project option in the Project Type form, and click Next.

Figure 2. "Add sources" window

During the Add Sources step you can create or import your source files. Click on the Create File button. You will see Create Source File dialog box. Name your VHDL file. Click OK. You can skip this step and add the sources later by choosing Add sources in Project Manager window. Make sure that VHDL is selected as target and simulator language.

Figure 3. "Default part" window

In the Default Part form choose the Board tab and select ZedBoard Zynq Evaluation and Development Kit. Click Next to review the Project Summary page. Define Module window will appear if the source file was created in the Wizard. Otherwise you will see it after pressing Add Source in Project Manager menu. For the new source file specify the entity and architecture names, port names, including their direction and range, if they are of vector type.

Figure 4. Define module window.

The new source file opens with the HDL Editor. The working space already contains a skeleton code. In order to complete the task of creating a 2-input logic AND element only one line of code is needed. It is underlined in Listing 1.

entity AND_gate is Port ( A : in STD_LOGIC; B : in STD_LOGIC; O : out STD_LOGIC);

end ANG_gate;

architecture Behavioral of ANG_gate is

begin

O A,

B => B, O => O );

A ................
................

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