HLS Tips and Tricks - Xilinx

Vivado HLS ? Tips and Tricks

Presented By Fr?d?ric Rivoallon Marketing Product Manager October 2018

? Copyright 2018 Xilinx

Vivado HLS

Algorithms

Abstracted C based descriptions Higher productivity

Concise code Optimized libraries Fast C simulation Automated simulation of generated RTL Interface synthesis (AXI-4)

Coding techniques

? Micro-architecture ? RAM adaptation ? Data type optimization

Design steps

? C sim ? C synthesis ? Co-sim

C / C++ OpenCL

Vivado HLS

Automated RTL verification

AXI I/F

Interface synthesis

RTL IP

Integration

IP Integrator

Platform Awareness

RTL

Vivado Synthesis, P&R

? Copyright 2018 Xilinx

Open Source HLS C++ Library

RTL IP

Vivado HLS Acceptance Grows...

5,000+ papers since 2014!

1370

High demand for deep learning accelerators on FPGAs

Software programmable FPGA SoCs become available

2000

Based on graph from Cornell University.

Year

? Copyright 2018 Xilinx

2013 2015 2017

Factors for Overall System Performance

Platform

Fixed Performance...

Off-chip memory, data links (e.g. PCIe)

Connectivity IPs

Compute Customization

Micro-architecture, parallelism, operators

Memory Adaptation

On-chip memory, shift registers, piping

Datatype Optimization

Customized data type (adjusted to requirement)

? Copyright 2018 Xilinx

Malleable Performance... Data Processing (RTL, HLS)

Connectivity IPs

Typically Xilinx IPs

FPGA

D D

R

Identify the Performance Challenge

Compute-bound or memory-bound? What kind of parallelism is required?

Algorithm Examples

Cornell University - Rosetta benchmarks:

? Copyright 2018 Xilinx

 ................
................

In order to avoid copyright disputes, this page is only a partial summary.

Google Online Preview   Download