Vitis High-Level Synthesis User Guide
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Vitis High-Level Synthesis User Guide
UG1399 (v2021.2) October 22, 2021
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Table of Contents
Section I: Getting Started with Vitis HLS.........................................................10
Chapter 1: Navigating Content by Design Process............................... 11
Chapter 2: Design Principles for Software Programmers................. 12
Three Paradigms for Programming FPGAs.......................................................................14 Combining the Three Paradigms....................................................................................... 21 Conclusion - A Prescription for Performance................................................................... 25
Chapter 3: Introduction to Vitis HLS............................................................. 28
Vitis HLS Memory Layout Model........................................................................................ 28 Basics of High-Level Synthesis............................................................................................40 Tutorials and Examples....................................................................................................... 46
Chapter 4: Vitis HLS Process Overview........................................................ 47
Enabling the Vivado IP Flow................................................................................................49 Enabling the Vitis Kernel Flow............................................................................................ 49 Default Settings of Vivado/Vitis Flows............................................................................... 50
Chapter 5: Launching Vitis HLS........................................................................ 52
Setting Up the Environment............................................................................................... 53 Overview of the Vitis HLS IDE............................................................................................. 53
Chapter 6: Creating a New Vitis HLS Project............................................ 57
Working with Sources.......................................................................................................... 64 Setting Configuration Options........................................................................................... 71 Specifying the Clock Frequency..........................................................................................74 Using the Flow Navigator....................................................................................................76
Chapter 7: Verifying Code with C Simulation...........................................78
Writing a Test Bench............................................................................................................ 81 Using the Debug View Layout............................................................................................ 88
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Output of C Simulation........................................................................................................ 89 Pre-Synthesis Control Flow................................................................................................. 89
Chapter 8: Synthesizing the Code...................................................................92
Synthesis Summary..............................................................................................................94 Output of C Synthesis........................................................................................................ 101 Improving Synthesis Runtime and Capacity................................................................... 102
Chapter 9: Analyzing the Results of Synthesis...................................... 103
Schedule Viewer ................................................................................................................ 103 Function Call Graph Viewer...............................................................................................107 Dataflow Viewer................................................................................................................. 109 Timeline Trace Viewer........................................................................................................111
Chapter 10: Optimizing the HLS Project....................................................113
Creating Additional Solutions........................................................................................... 113 Adding Pragmas and Directives....................................................................................... 115
Chapter 11: C/RTL Co-Simulation in Vitis HLS........................................ 122
Output of C/RTL Co-Simulation........................................................................................ 125 Automatically Verifying the RTL....................................................................................... 126 Analyzing RTL Simulations................................................................................................ 130 Cosim Deadlock Viewer..................................................................................................... 132 Debugging C/RTL Co-Simulation..................................................................................... 134
Chapter 12: Exporting the RTL Design....................................................... 138
Running Implementation..................................................................................................141 Implementation Report.....................................................................................................143 Output of RTL Export......................................................................................................... 145 Archiving the Project..........................................................................................................146
Chapter 13: Running Vitis HLS from the Command Line.................148
Section II: Vitis HLS Hardware Design Methodology..............................150
Chapter 14: Introduction to the Methodology Guide........................151
Chapter 15: Designing Efficient Kernels....................................................152
Chapter 16: Vitis HLS Coding Styles............................................................. 155
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Unsupported C/C++ Constructs....................................................................................... 155 Functions............................................................................................................................. 159 Loops................................................................................................................................... 161 Arrays...................................................................................................................................169 Data Types...........................................................................................................................177 C++ Classes and Templates...............................................................................................214 Assertions............................................................................................................................220 Examples of Hardware Efficient C++ Code......................................................................223
Chapter 17: Defining Interfaces.................................................................... 242
Introduction to Interface Synthesis................................................................................. 242 Interfaces for Vitis Kernel Flow.........................................................................................243 Interfaces for Vivado IP Flow............................................................................................ 249 AXI Adapter Interface Protocols.......................................................................................254 Port-Level I/O Protocols.................................................................................................... 291 Block-Level Control Protocols........................................................................................... 301 Managing Interfaces with SSI Technology Devices....................................................... 304
Chapter 18: Optimization Techniques in Vitis HLS.............................. 306
Controlling the Reset Behavior........................................................................................ 308 Optimizing for Throughput...............................................................................................311 Optimizing for Latency...................................................................................................... 351 Optimizing for Area........................................................................................................... 354 Optimizing Logic................................................................................................................ 361 Optimizing AXI System Performance.............................................................................. 364 Adding RTL Blackbox Functions....................................................................................... 396
Section III: Vitis HLS Command Reference...................................................410
Chapter 19: vitis_hls Command......................................................................411
hls_init.tcl.............................................................................................................................412
Chapter 20: Project Commands......................................................................413
add_files...............................................................................................................................413 close_project....................................................................................................................... 414 close_solution..................................................................................................................... 415 cosim_design...................................................................................................................... 416 cosim_stall........................................................................................................................... 418 create_clock.........................................................................................................................418
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csim_design.........................................................................................................................419 csynth_design..................................................................................................................... 420 delete_project..................................................................................................................... 421 delete_solution................................................................................................................... 422 enable_beta_device............................................................................................................ 422 export_design..................................................................................................................... 423 get_clock_period................................................................................................................. 425 get_clock_uncertainty........................................................................................................ 425 get_files............................................................................................................................... 426 get_part............................................................................................................................... 426 get_project.......................................................................................................................... 427 get_solution........................................................................................................................ 427 get_top.................................................................................................................................428 help...................................................................................................................................... 428 list_part................................................................................................................................ 429 open_project....................................................................................................................... 430 open_solution..................................................................................................................... 431 open_tcl_project................................................................................................................. 432 set_clock_uncertainty......................................................................................................... 433 set_part................................................................................................................................ 434 set_top................................................................................................................................. 435
Chapter 21: Configuration Commands...................................................... 436
config_array_partition........................................................................................................436 config_compile....................................................................................................................437 config_dataflow.................................................................................................................. 439 config_debug...................................................................................................................... 441 config_export...................................................................................................................... 441 config_interface.................................................................................................................. 444 config_op............................................................................................................................. 447 config_rtl..............................................................................................................................450 config_schedule.................................................................................................................. 451 config_storage.................................................................................................................... 452 config_unroll....................................................................................................................... 453
Chapter 22: Optimization Directives...........................................................454
set_directive_aggregate.................................................................................................... 454 set_directive_alias...............................................................................................................455
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