Introduction to SystemVerilog - Computer Architecture Stony Brook Lab
嚜燙pring 2018 :: CSE 502
Introduction to
SystemVerilog
Nima Honarmand
(Slides adapted from Prof. Milder*s ESE-507 course)
Spring 2018 :: CSE 502
First Things First
? SystemVerilog is a superset of Verilog
每 The SystemVeriog subset we use is 99% Verilog + a few
new constructs
每 Familiarity with Verilog (or even VHDL) helps but is not
necessary
? SystemVerilog resources and tutorials on the course
※Assignments§ web page
Spring 2018 :: CSE 502
Hardware Description Languages (HDL)
? HDLs are used for a variety of purposes in hardware design
每
每
每
每
每
Functional simulation
Timing simulation
Hardware synthesis
Testbench development
#
? Many different features to accommodate all of these
每 We focus on functional simulation
? With HDLs, you describe hardware in one of two styles (usually)
每 Structural model (network of gates and transistors)
每 Behavioral model (high-level statements such as assignments, if, while, #)
? We use behavioral modeling for the course project
每 Much simpler than designing with gates
Spring 2018 :: CSE 502
HDLs vs. Programming Languages (1)
? Have syntactically similar constructs:
每 Data types, variables, operators, assignments, if statements,
loops, #
? But very different mentality and semantic model
? Statements are evaluated in parallel (unless specified
otherwise)
每 Statements model hardware
每 Hardware is inherently parallel
Reset your mind! You are a HW developer now.
Stop thinking like a SW programmer!
Spring 2018 :: CSE 502
HDLs vs. Programming Languages (2)
? Software programs are organized as a set of
subroutines
每 Subroutines call each other, passing arguments and
return values
每 When in callee, caller*s execution is paused
? Hardware descriptions are organized as a hierarchy
of hardware modules
每 A hierarchy of module instances connected to each
other using wires
每 Modules are active at the same time
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