Innovative Uses of SystemVerilog Bind Statements within Formal Verification
Innovative Uses of SystemVerilog Bind Statements within Formal Verification
Xiushan Feng and Christopher Starr Samsung Austin R&D Center
Agenda
? Introduction
? SystemVerilog bind statement ? Formal verification and SystemVerilog Assertions (SVAs)
? Our use cases of bind statements within formal verification
? Sequential equivalence checking for clock gating (SEQ) ? Data-Path Verification (DPV) ? Formal Property Verification (FPV)
2
Introduction: SystemVerilog Bind
? Syntax
bind_directive ::= bind bind_target_scope [: bind_target_instance_list] bind_instantiation ;
| bind bind_target_instance bind_instantiation ;
scope or instance of module|interface
TARGET
bind_instantiation ::= program_instantiation
| module_instantiation | interface_instantiation | checker_instantiation
? Usage
? Add verification code into RTL design ? Verification code can be separated from RTL ? Very uncommon to be used by RTL for synthesis
module|program|interface|checker FOO ... end{module|program|interface|checker} bind TARGET FOO #(...) FOO_inst (.*);
3
Formal Verification is Assertion-Based
? M, s, a |= p . For all state s of a model M (e.g., a circuit), property p is true under the assumptions of a
? Properties/assumptions are written in assert/assume type assertions ? Not all assertions can be easily created with available design signals
? RTL modeling is required to simplify SVAs ? It is convenient to add some extra logic for debug ? Complicated helper logic should be outside RTL design if possible
4
Formal Tools Can Manipulate Designs
? A snip_driver example
snip_driver FOO
FOO
X
$driver(FOO) FOO
With snip_driver and assumptions, we can manipulate design logic
5
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