Modeling FIFO Communication Channels Using SystemVerilog Interfaces

Modeling FIFO Communication Channels Using

SystemVerilog Interfaces

Stuart Sutherland

Sutherland HDL, Inc.

stuart@sutherland-

ABSTRACT

The Verilog Hardware Description Language (Verilog HDL) does not have a direct equivalent to

SystemC channels.

These channels are often used for modeling abstract, high-level

communications between modules. This paper shows how the SystemVerilog extensions to

Verilog can be used to model high-level communication channels.

SystemVerilog extends the Verilog HDL with a powerful interface construct. This construct

provides a way to encapsulate the communication between the major blocks of a design.

Interfaces can be used for more than just data encapsulation, however. An interface can also

contain procedural code, tasks and functions. This paper provides a brief tutorial on

SystemVerilog interfaces, and then delves into one way in which interfaces can be used for highlevel modeling. A FIFO channel is used as the basis for examples in this paper, but the concepts

presented can be applied to other types of communication channels, such as a mutex channel. The

FIFO behavior is modeled using other powerful SystemVerilog constructs: mailboxes and queues.

The interface FIFO channel is modeled to be reconfigurable; it can be configured to pass data of

any data type, including integers, reals, vectors of any size, and user-defined types. The paper also

discusses synthesizing SystemVerilog interfaces and the modeling constructs used in the

examples shown.

SNUG Boston 2004

1 Modeling FIFO Channels Using SystemVerilog Interfaces

Table of Contents

1.0 SystemC channels versus SystemVerilog interfaces .............................................................3

2.0 SystemVerilog interface tutorial ............................................................................................4

2.1 Referencing signals defined within an interface ...........................................................5

2.2 Interface module port declarations (modports) .............................................................5

2.3 Selecting modports .......................................................................................................5

2.4 Interface methods ..........................................................................................................7

2.5 Interface processes ........................................................................................................8

2.6 Parameterized SystemVerilog interfaces ......................................................................8

3.0 Modeling FIFO channels using SystemVerilog mailboxes ...................................................9

3.1 Overview of SystemVerilog mailboxes ........................................................................9

3.2 A FIFO channel using mailboxes ...............................................................................11

3.3 Connecting and using the interface channel ...............................................................13

3.4 Synthesis considerations with mailboxes ...................................................................14

4.0 Modeling FIFO channels using SystemVerilog queues ......................................................15

4.1 Overview of SystemVerilog queues ...........................................................................15

4.2 An abstract FIFO channel using queues .....................................................................16

4.3 Connecting and using the interface channel ...............................................................17

4.4 Synthesis considerations with queues .........................................................................17

5.0 A synthesizable FIFO channel using queues .......................................................................18

5.1 Connecting and using the interface channel ...............................................................21

5.2 Synthesis considerations .............................................................................................21

6.0 Conclusions ..........................................................................................................................22

7.0 Future work ..........................................................................................................................23

8.0 References ............................................................................................................................24

9.0 About the author ..................................................................................................................24

List of Figures and Examples

Figure 1:

Inter-module communication using a FIFO ..............................................................4

Figure 2:

Verilog Ports vs. Interface Ports ...............................................................................5

Example 1: SystemVerilog Interface with modports ...................................................................6

Example 2: Interface modport selection as part of the module instance ......................................7

Example 3: Interface modport selection as part of the module definition ...................................7

Example 4: Interface methods imported into modules ................................................................8

Example 5: Calling imported interface methods ..........................................................................9

Example 6: Interface with procedural code .................................................................................9

Example 7: Parameterized interface FIFO size ..........................................................................10

Example 8: Parameterized interface data types .........................................................................10

Figure 3:

UNI and NNI ATM switch data packets ................................................................13

Example 9: SystemVerilog definitions for UNI and NNI ATM switch data packets ................13

Example 10: Complete SystemVerilog FIFO interface channel using SystemVerilog mailboxes14

Example 11: Netlist connecting two modules using the FIFO interface channel .........................15

Example 12: Abstract SystemVerilog FIFO interface channel using SystemVerilog queues .....18

Example 13: Synthesizable SystemVerilog FIFO interface channel using queues ......................20

SNUG Boston 2004

2 Modeling FIFO Channels Using SystemVerilog Interfaces

1.0 SystemC channels versus SystemVerilog interfaces

SystemC provides channels and interfaces for communication between modules. A SystemC

channel encapsulates how information is transferred between modules. A SystemC interface

defines a set of methods (functions) for a channel. These methods are used to send and receive

information through a channel, and to probe and control a channel. Channels can be user defined,

and can be built from other SystemC constructs, such as ports, module instances, other channels,

and processes. The current SystemC standard, 2.0.1[1] also includes a number of pre-defined

channels, such as sc_signal, sc_fifo, sc_mutex, and sc_sempahore. In general, these predefined SystemC channels are not considered to be synthesizable[2]. They do not contain the

level of logic detail required for synthesis tools to realize the intended hardware implementation.

SystemVerilog adds an interface construct to the Verilog language. A SystemVerilog interface is

essentially the same as a SystemC channel. An interface encapsulates the communication

information between Verilog modules. This encapsulation can include the module port

definitions, tasks, functions, always blocks, continuous assignments, assertions, and other

modeling constructs. Interfaces can also include instances of other interfaces, allowing more

complex, hierarchical interfaces to be modeled.

Unlike SystemC, SystemVerilog does not provide a set of pre-defined communication channels.

SystemVerilog provides the general purpose interface construct, enabling designers to model any

type of communication functionality. SystemVerilog also provides a number of powerful

extensions to Verilog that make it easy to model complex communications between modules at a

higher level of abstraction than is possible with Verilog. These extensions include semaphores,

mailboxes and queues.

This paper shows how the functionality of one of the more complex SystemC built-in channels, a

FIFO (First-In, First-Out), can be easily modeled using SystemVerilog interfaces. FIFOs are

typically used to communicate data between design blocks that are operating with different,

asynchronous clocks. Both high-level abstract versions of a communication channel are

presented, as well as synthesizable versions. The concepts shown in this paper can be readily

adapted to a variety of other communication channel types.

Figure 4. Inter-module communication using a FIFO

Master

module

packet

data packet

write

pointer

write

method

SNUG Boston 2004

Slave

module

BUS interface

data packet

data packet

read

method

read

pointer

packet

3 Modeling FIFO Channels Using SystemVerilog Interfaces

2.0 SystemVerilog interface tutorial

The basic building block for a SystemVerilog interface is the keyword pair interface...

endinterface. This keyword pair is used to define a separate structural block, similar to a

Verilog module. In its most basic form, an interface simply encapsulates the signals that are used

to communicate between Verilog modules. The interface block is then used as a module port,

replacing multiple discrete ports for each communication net. Figure 5 contrasts module

interconnections using Verilog module ports with a basic SystemVerilog interface. Observe the

usage of the interface...endinterface keyword pair, and how the MASTER and SLAVE modules

use the interface as a module port.

Figure 5. Verilog Ports vs. Interface Ports

Module Communication Using

Verilog Ports

MASTER

module

SLAVE

module

Module Communication Using

SystemVerilog Interfaces

MASTER

module

BUS

data

data

address

address

request

request

grant

grant

ready

ready

clock

SLAVE

module

clock

¡°BUS¡± is the

module MASTER (input

clock,

inout [31:0] data,

output [15:0] address,

output

request,

input

grant,

input

ready );

...

endmodule

module SLAVE

(input

clock,

inout [31:0] data,

input [15:0] address,

input

request,

output

grant,

output

ready );

...

endmodule

module top (input clock);

wire [31:0] data,

wire [15:0] address,

wire

request, grant, ready;

MASTER

SLAVE

interface BUS ;

interface name

wire

[31:0] data,

logic [15:0] address,

logic

request, grant, ready;

endinterface

module MASTER (interface io_bus);

...

¡°io_bus¡± is the

endmodule

module port name

module SLAVE (interface io_bus);

...

endmodule

module top (input clock);

¡°io¡± is the

BUS

io ();

interface

MASTER i1 (io, clock); instance name

SLAVE

i2 (io, clock);

endmodule

i1 (clock, data, address,

request, grant, ready);

i2 (clock, data, address,

request, grant, ready);

endmodule

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4 Modeling FIFO Channels Using SystemVerilog Interfaces

2.1 Referencing signals defined within an interface

Modules that are connected to an interface can reference the interface signals by using a relative

hierarchical path name. The path name is formed by prepending the name of the interface port to

the signal name. For example:

module MASTER (interface io_bus);

always @(io_bus.request)

...

// "io_bus" is the port name

// "request" is inside the interface

2.2 Interface module port declarations (modports)

Each module connected to an interface may need to see a different view of the signals within the

interface. In the example above, the request signal is an output from the MASTER module, and is

an input to the SLAVE module. SystemVerilog interfaces provide a means to define different views

of an interface. The definition is made within the interface, using the modport keyword, which is

an abbreviation for module port. An interface can have any number of modport definitions, each

describing a different view of the signals within the interface. Examples of two modport

declarations are:

Example 14. SystemVerilog Interface with modports

interface BUS ;

wire

[31:0] data;

logic [15:0] address;

logic

request, grant, ready;

modport master_ports (inout

output

output

input

input

data,

address,

request,

grant,

ready );

modport slave_ports

data,

address,

request,

grant,

ready );

(inout

input

input

output

output

endinterface

2.3 Selecting modports

SystemVerilog provides two ways to specify which modport a module interface port should use:

? As part of the interface connection to a module instance

? As part of the module port declaration in the module definition

Selecting the modport at the module instance

When a module is instantiated and an instance of an interface is connected to a module instance

port, the specific modport of the interface can be specified, as illustrated in Example 15.

SNUG Boston 2004

5 Modeling FIFO Channels Using SystemVerilog Interfaces

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