SystemVerilog Ports & Data Types For Simple, Efficient and Enhanced HDL ...
SystemVerilog Ports & Data Types For Simple, Efficient and Enhanced HDL
Modeling
Clifford E. Cummings
Sunburst Design, Inc.
cliffc@sunburst-
Abstract
Verilog-2001 introduced an enhanced and abbreviated
method to declare module headers, ports and data types.
The Accellera SystemVerilog effort will further enhance
Verilog design by abbreviating the capability to
instantiate modules with implicit port connections and
interface types. These capabilities and additional
complimentary enhancements are detailed in this paper.
1.
Introduction
Figure 1 - muxff Block Diagram
To declare, or not to declare, that is the question!
Verilog-1995[1] had verbose and redundant port
declaration requirements. Verilog-2001[2] introduced the
¡°ANSI-C¡±-style enhancement to remove port declaration
redundancy from the Verilog language. Accellera
SystemVerilog proposals will further enhance port
declarations with the introduction of interface
declarations. The evolution of and enhancements to
Verilog port declarations are detailed in this paper.
module muxff1 (q, d, clk, ce, rst_n);
output q;
input d, clk, ce, rst_n;
reg
q;
wire
y;
always @(posedge clk or negedge rst_n)
if (!rst_n) q ................
................
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