Static Random Access Memories (SRAM)

[Pages:9]EE371 Spring 1999

Static Random Access Memories (SRAM)

Birdy Amrutur amrutur@hpl.

EE371 Spring 1999

Key features of SRAMs

Holds data statically:

As long as power is supplied to the chip, the data remains.

Data randomly accessible: ReadData = Memory[ Address ] Memory[ Address ] = WriteData

EE371 Spring 1999

SRAMs Used as:

Embedded memory, e.g.:

First and second level caches in processors

Data buffers in various DSP chips

Standalone SRAMs: Caches in computer systems Main memory in low power applications

Typical sizes: Embedded: upto 1Mbit Standalone: upto 16Mbit

EE371 Spring 1999

The system level view of SRAMs

Asynchronous interface

tAC

address

tAA

Ai

Aj

data in r/w

M [ 0 .. 2n ]

data out

M [ Ai ]

Used for stand alone SRAM chips

Synchronous interface

tsu

tcyc

address r/w data out data in clk

address data in r/w clk

M [ 0 .. 2n ]

data out

Ai

Aj

address

r/w

M [ Ai ] data out

Used for embedded and standalone SRAMs

data in

EE371 Spring 1999

SRAM Architecture

Row decoder

2m word line

2n m

Address input n

Column decoder

Read enable

Sense en Write en Read-write control

bitline

Column Mux Sense amplifier Write driver

Data in Data out

EE371 Spring 1999

b

CMOS SRAM cell

b wp

wa

Vdd

wp wa

wordline a) Static cell

wn

wn

b) 6T CMOS cell

c) 4T poly-R cell

d) 6T poly-PMOS cell

EE371 Spring 1999

Reading a cell

b Cb

0 a

Icell

wl

b

1

wl

a

b,b

v

a

a

Icell * v =

Cb

Sense Amplifier D

EE371 Spring 1999

Writing a cell

b

b

wl

0

1

b

a

a

b

Cb

a

Icell

a

wl

D = 0 write

D = 1

EE371 Spring 1999

Pre

Bitline precharge and load

Pre

Pre

cell wl

Important to equalize bitline voltage before reads

cell wl

cell wl

b

b

b,b

Pre wl

Precharged to Vdd . Precharge shut off during reads

and writes

Use with latch style sense amps

b,b

Pre

v

wl

b,b

Pre wl

vdd vdd -vtn v

Bitline voltage clamped during reads. Precharge to an Nmos threshold below supply

Use with current sense amps

Useful with current mirror sense amps (Cant operate with low supply)

EE371 Spring 1999

Sense amplifiers

Need to amplify input bitline swing of ~100mV to full digital levels.

b

b

b

b

Sense enable

Sense clock

Current mirror amplifier

Latch type amplifier

EE371 Spring 1999

1

Decoders

16

1

16 word driver

Logically an n-input AND function.

Enables the "Random Access" portion

CL

of RAMs.

Row decoder in the critical path of the SRAM access.

Could contribute upto 40% of the delay and power

256

Large decoders implemented hierarchically.

A0A1A2A3

A0 A1 A3

An 8 to 256 decoder

4 to 16 predecoder

EE371 Spring 1999

Sram Partitioning

Divided word line Architecture

global word line

block select

bitlines

local word line

address

IO lines

global sense amp

dout din

Use higher level metal for global word lines

local senseamp

EE371 Spring 1999

Bitline partitioning

Wordline drivers Wordline drivers

256 512

256

sense amps

Single Level Mux Use higher level metal for global bitlines

Global Bitlines

Two Level Mux

EE371 Spring 1999

Partioning summary

Partioning involves a trade off between area, power and speed

For high speed designs, use short blocks(e.g 64 rows x 128 columns ) Keep local bitline heights small

For low power designs use tall narrow blocks (e.g 256 rows x 64 columns) Keep the number of columns same as the access width to minimize wasted power

EE371 Spring 1999

b wp

wa a wd

wl

CMOS SRAM cell design-1

Vdd

b wp

wa a

wd

Problem: Find wa, wd, wp such that 1) minimize cell area 2) obtain good read and write cell margins 3) good soft error immunity 4) good cell read current

in that order

Conflicting goals!

Vdd

a Vdd

wp

wa

a

a

wd Vdd

Static Noise Margin a

EE371 Spring 1999

CMOS SRAM cell design-2

Read Stability

Vdd

b wp

wa a (=0)

b wp

wa (1=) a

wd

wd

wl

Usually Cbit is very big compared to internal node capacitances

Cell will flip if the "0" node bounces high enough to cause the "1" node to discharge

Cbit

Simulate for worst case scenario with threshold and size mismatches in the cell which aids in

flipping

To obtain good stability :

=

wd * ( Vdd - Vtn ) 2 wa * ( Vdd - Vtn ) 2

=

wd wa

> 2.5

Vdd

wp wa*1.1

a + - wd Vt Vdd

Vdd Vdd

wp wa

a

+Vt- wd*1.1

wl b,b

a a

Dynamic read noise margin

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