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Memory Design

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Adapted from J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits, 2nd ed. Copyright 2003 Prentice Hall/Pearson.

ECE 261

James Morizio

1

Semiconductor Memory Classification

Read-Write Memory

Non-Volatile Read-Write

Memory

Read-Only Memory

Random Access

SRAM DRAM

Non-Random Access

FIFO LIFO Shift Register CAM

EPROM

2

E PROM

FLASH

Mask-Programmed Programmable (PROM)

ECE 261

James Morizio

2

Memory Timing: Definitions

Read cycle

READ WRITE

Read access

Read access Data valid

Write cycle Write access

DATA

Data written

ECE 261

James Morizio

3

Memory Architecture:

M bits Decoders

M bits

S0

Word 0

S1 S2

Word 1 Word 2

A0

Storage

cell

A1

S0 Word 0 Word 1 Word 2

Storage cell

NworSdNs2 2

SN2 1

Word N 2 2 Word N 2 1

AK2 1 K 5 log2N

DecoderWord N2 2

Word N 2 1

Input-Output (M bits)

Input-Output (M bits)

Intuitive architecture for N x M memory Decoder reduces the number of select signals

Too many select signals: N words == N select signals

K = log2N

ECE 261

James Morizio

4

Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH

AK AK1 1

2L 2 K

Bit line

Storage cell Word line

Row Decoder

AL2 1

M. 2K Sense amplifiers / Drivers

A0 AK2 1

Column decoder

Amplify swing to rail-to-rail amplitude

Selects appropriate word

Input-Output (M bits)

ECE 261

James Morizio

5

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