Memory Structures - Docència
Memory Structures
Ramon Canal NCD - Master MIRI
Slides based on:Introduction to CMOS VLSI Design. D. Harris
NCD - Master MIRI
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Outline
? Memory Arrays ? SRAM Architecture
? SRAM Cell ? Decoders ? Column Circuitry ? Multiple Ports
? Serial Access Memories
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Memory Arrays
Memory Arrays
Random Access Memory
Serial Access Memory Content Addressable Memory (CAM)
Read/Write Memory (RAM)
(Volatile)
Read Only Memory (ROM)
Shift Registers
(Nonvolatile)
Queues
Static RAM (SRAM)
Dynamic RAM (DRAM)
Serial In Parallel Out
(SIPO)
Parallel In Serial Out
(PISO)
First In First Out (FIFO)
Last In First Out (LIFO)
Mask ROM
Programmable ROM
(PROM)
Erasable Programmable
ROM (EPROM)
Electrically Erasable Programmable
ROM (EEPROM)
Flash ROM
NCD - Master MIRI
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Array Architecture
? 2n words of 2m bits each
? If n >> m, fold by 2k into fewer rows of more columns
wordlines bitline conditioning bitlines
row decoder
memory cells: 2n-k rows x 2m+k columns
n-k k
n column decoder
2m bits
column circuitry
? Good regularity ? easy to design
? Very high density if good cells are used
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12T SRAM Cell
? Basic building block: SRAM Cell
? Holds one bit of information, like a latch ? Must be read and written
? 12-transistor (12T) SRAM cell
? Use a simple latch connected to bitline ? 46 x 75 unit cell
bit write write_b read read_b
NCD - Master MIRI
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